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TNETV2840ENGGU 数据表(PDF) 24 Page - Texas Instruments |
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TNETV2840ENGGU 数据表(HTML) 24 Page - Texas Instruments |
24 / 91 page Functional Overview 24 December 1999 − Revised October 2008 SPRS122F 3.1 Memory Each 5441 DSP subsystem maintains the peripheral register memory map and interrupt location/priorities of the standard 5421. Each individual subsystem CPU memory map is illustrated in Figure 3−3 through Figure 3−6. The arbitration and access for local program/data memory and local data memory is based on a 16K-word block size. The arbitration and access for all the shared memory is based on a 32K-word block size. 3.1.1 Memory Maps Figure 3−3 through Figure 3−6 illustrate the CPU memory maps for subsystem A through subsystem D. Figure 3−7 provides a detailed memory map of the local data memory relative to CPU subsystems A, B, C, and D. Page 0 Data Memory Page 1 8000h Page 2 FFFFh Page 3 0000h MPDA Page 0 Data Memory Page 1 Program Memory Page 2 Page 3 0000h 8000h FFFFh : reserved Program Memory Memory Map with OVLY = 1 MPDA MPDA MPDA MPDA MPAB3 MPAB0 MPAB1 MPAB2 MPAB3 MPDA MPAB3 MPAB3 MPAB3 MPAB0 MPAB1 MPAB2 Memory Map with OVLY = 0 MDA0 or MDA1 MDA0 or MDA1 NOTES: A. MPDA: local program/data memory in subsystem A B. MDA: local data memory in subsystem A. MDA is controlled by the data memory map register (DMMR). DMMR=0, MDA0 is mapped in 8000h − FFFFh. DMMR=1, MDA1 is mapped in 8000h − FFFFh. C. MPAB: shared program memory in subsystems A and B Figure 3−3. Subsystem A CPU Memory Map |
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