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CAT1162J-28TE13 数据表(PDF) 9 Page - Catalyst Semiconductor |
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CAT1162J-28TE13 数据表(HTML) 9 Page - Catalyst Semiconductor |
9 / 12 page 9 CAT1161/2 Doc No. 3002, Rev. D Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1161/2 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT1161/2 is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent memory array programming. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT1161/2 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. Read Operations The READ operation for the CAT1161/2 is initiated in the same manner as the write operation with one exception, that R/ W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. SCL SDA 8TH BIT STOP NO ACK DATA OUT 89 SLAVE ADDRESS S A C K DATA N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T Figure 9. Immediate Address Read Timing |
类似零件编号 - CAT1162J-28TE13 |
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类似说明 - CAT1162J-28TE13 |
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