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LM98519 数据表(PDF) 9 Page - Texas Instruments |
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LM98519 数据表(HTML) 9 Page - Texas Instruments |
9 / 57 page LM98519 www.ti.com SNAS425C – OCTOBER 2007 – REVISED OCTOBER 2014 Electrical Characteristics (continued) The following specifications apply for VDDA = VDDD = VDDO = 3.3 V; FMCLK = 65 Ms/s and TA =+25°C unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX. All other limits apply for TA =+25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SH3 Mode – ADC Rate MCLK 9 13 SH2 Mode 10.5 14.5 MCLK high to SAMPLE high tMCS_MIN ns(5) (Minimum)(4) SH1b Mode 2.4 5 CDSb Mode 1.8 4 SH3 Mode – ADC Rate MCLK 0.7 3.5 SH2 Mode –0.7 3 HOLD high to MCLK high tHMC_MIN ns(5) (Minimum)(4) SH1b Mode –2.1 2 CDS Mode –3.1 1 MCLK high to HOLD high tMCH_MIN SH3 Mode – ADC Rate MCLK 1 5 ns (Minimum)(4) Aperture delay 4 5 6.9 tAD ns Aperture delay variation 0.2 1 tBCLPINB, CLPIN/BLKCLP Pulse Width (high or low) 2 tMCLK tBLKCLP tIS CLPIN/BLKCLP Setup 3 ns tIH CLPIN/BLKCLP Hold 3 ns 6 Channel mode 16 tC_B CLPIN neg. edge to BLKCLP start Pixels 3 Channel mode 10 6 Channel Mode 6 Channel Mode, ADC Rate MCLK 11 tLAT(1) tMCLK Channel 1 Latency 6 Channel Mode, Pixel Rate MCLK 5 6 Channel Mode 6 Channel Mode, ADC Rate MCLK 12 tLAT(2) tMCLK Channel 2 Latency 6 Channel Mode, Pixel Rate MCLK 5.5 3 Channel Mode ADC=Pixel Rate tLAT 3 Channel Mode Latency 11 tMCLK MCLK Pixel Rate MCLK: 6 Channel Mode – Channel 1 2 5.2 8 ns(6) 6 Channel Mode – Channel 2 2 5 8 tOD Output Data Delay ADC Rate MCLK: 6 Channel Mode – Channel 1 3 6 9 ns 6 Channel Mode – Channel 2 3 6 9 3 Channel Mode 2 5.4 9 (4) Refer to Sampling Timing Diagrams (5) Measured with AFEPHASE = 11. For other AFEPHASE settings,these sample input timings will shift earlier with respect to MCLK as follows. (tHMC will increase by these amounts, tMCH will decrease by these amounts): (a) AFEPHASE = 10 – Earlier by ¼ pixel period (b) AFEPHASE = 01 – Earlier by ½ pixel period (c) AFEPHASE = 00 – Earlier by ¾ pixel period (6) In Pixel Rate MCLK mode, the output data delay for Channel 2 data may be different under certain conditions of low MCLK duty cycle (< 50%). In that case the approximate output data delay tOD will increase by the following: (50 – MCLK Duty Cycle Percent)/100 * TMCLK Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LM98519 |
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类似说明 - LM98519 |
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