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SN74LVC1G07DRL 数据表(PDF) 9 Page - Texas Instruments |
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SN74LVC1G07DRL 数据表(HTML) 9 Page - Texas Instruments |
9 / 38 page A Y 9 SN74LVC1G07 www.ti.com SCES296AD – FEBRUARY 2000 – REVISED MAY 2016 Product Folder Links: SN74LVC1G07 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The SN74LVC1G07 device contains one open-drain buffer with a maximum sink current of 32 mA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The DPW package technology is a major breakthrough in IC packaging. The DPW 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm. 8.2 Functional Block Diagram 8.3 Feature Description • Wide operating voltage range. – Operates from 1.65 V to 5.5 V. • Allows down voltage translation. • Inputs and outputs accept voltages to 5.5 V. • Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V. 8.4 Device Functional Modes Function Table INPUT A OUTPUT Y L L H Z |
类似零件编号 - SN74LVC1G07DRL |
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类似说明 - SN74LVC1G07DRL |
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