FPGA

GTL2014PW

LVTTL

GTL

Chipset

R2

R1

VTT

R

1

2

3

4

5

6

7

8

9

10

11

12

13

14

DIR

B0

B1

VREF

B2

B3

GND

GND

A3

A2

GND

A1

A0

VCC

3.3 V

Port_B to Port_A

GTL to LVTTL

3.3 V

2*VTT/3

1.0 V

GND

75

49.9

100

VCC

Vref

VTT

DIR

R

R1

R2

SN74GTL2014

www.ti.com

SCLS746A – FEBRUARY 2014 – REVISED OCTOBER 2014

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

GTL2014 is the voltage translator for GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+. Please find the

reference schematic and recommend value for passive component in the Typical Application.

9.2 Typical Application

9.2.1 GTL–/GTL/GTL+ to LVTTL

Select appropriate VTT/VREF based upon GTL–/GTL/GTL+. The parameters in Recommended Operating

Conditions are compliant to the GTL specification.

Figure 5. Application Diagram for GTL to LVTTL

Copyright © 2014, Texas Instruments Incorporated

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