SN74AUP1T50 datasheet(1/15 Pages) TI1

部件名	SN74AUP1T50

功能描述	LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER BUFFER GATE

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制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

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SN74AUP1T50

www.ti.com

SCES844A – OCTOBER 2012 – REVISED MARCH 2013

LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE

SCHMITT-TRIGGER BUFFER GATE

Check for Samples: SN74AUP1T50

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FEATURES

•

Single-Supply Voltage Translator

•

More Gate Options Available at

www.ti.com/littlelogic

•

Output Level Up to Supply VCC CMOS Level

•

ESD Performance Tested Per JESD 22

–

1.8 V to 3.3 V (at VCC = 3.3 V)

–

2000-V Human-Body Model

–

2.5 V to 3.3 V (at VCC = 3.3 V)

(A114-B, Class II)

–

1.8 V to 2.5 V (at VCC = 2.5 V)

–

1000-V Charged-Device Model (C101)

–

3.3 V to 2.5 V (at VCC = 2.5 V

•

Schmitt-Trigger Inputs Reject Input Noise and

DCK PACKAGE

Provide Better Output Signal Integrity

(TOP VIEW)

•

Ioff Supports Partial Power Down (VCC = 0 V)

•

Very Low Static Power Consumption:

0.1 µA

•

Very Low Dynamic Power Consumption:

0.9 µA

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

Pb-Free Packages Available: SC-70 (DCK)

2 x 2.1 x 0.65 mm (Height 1.1 mm)

DESCRIPTION/ORDERING INFORMATION

The SN74AUP1T50 performs the Boolean function Y = A with designation for logic-level translation applications

with output referenced to supply VCC.

AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in

operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V

VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external

controllers or processors.

Schmitt-trigger inputs (

ΔVT = 210 mV between positive and negative input transitions) offer improved noise

immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger

inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile

applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of

the device. No damage occurs to the device under these conditions.

The SN74AUP1T50 is designed with optimized current-drive capability of 4 mA to reduce line reflections,

overshoot, and undershoot caused by high-drive outputs.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

类似零件编号 - SN74AUP1T50

制造商	部件名	数据表	功能描述
Texas Instruments	SN74AUP1T57	309Kb / 17P	[Old version datasheet] SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS
	SN74AUP1T57	933Kb / 24P	[Old version datasheet] SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS
	SN74AUP1T57	934Kb / 24P	[Old version datasheet] SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS
	SN74AUP1T57DBVR	933Kb / 24P	[Old version datasheet] SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS
	SN74AUP1T57DBVR	934Kb / 24P	[Old version datasheet] SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR WITH NINE CONFIGURABLE GATE LOGIC FUNCTIONS

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类似说明 - SN74AUP1T50

制造商	部件名	数据表	功能描述
Texas Instruments	SN74AUP1T17	164Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER BUFFER GATE
	SN74AUP1T14	761Kb / 14P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER INVERTER GATE
	SN74AUP1T14	164Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER INVERTER GATE
	SN74AUP1T157	283Kb / 13P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT SCHMITT-TRIGGER BUFFER MULTIPLEXER (NONINVERTED)
	SN74AUP1T158	283Kb / 13P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT SCHMITT-TRIGGER BUFFER MULTIPLEXER (INVERTED)
	SN74AUP1T17	820Kb / 18P	[Old version datasheet] 3.3-V CMOS Output Single Schmitt-Trigger Buffer Gate
	SN74AUP1T00	164Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT POSITIVE-NAND GATE
	SN74AUP1T02	164Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT,SINGLE 2-INPUT POSITIVE-NOR GATE
	SN74AUP1T04	164Kb / 11P	[Old version datasheet] LOW POWER,1.8/2.5/3.3-V INPUT,3.3-V COMS OUTPUT, SINGLE INVERTER GATE
	SN74AUP1T08	167Kb / 11P	[Old version datasheet] LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT POSITIVE-AND GATE

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