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SN74AUP1T34QDCKRQ1 数据表(PDF) 10 Page - Texas Instruments |
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SN74AUP1T34QDCKRQ1 数据表(HTML) 10 Page - Texas Instruments |
10 / 18 page LEGEND VIA to Power Plane (Inner Layer) VIA to GND Plane (Inner Layer) Polygonal Copper Pour 1 2 3 4 5 VCCA A GND B VCCB SN74AUP1T34-Q1DCK (Top View) From Source Bypass Capacitor To Destination Bypass Capacitor 10 SN74AUP1T34-Q1 SCES852A – DECEMBER 2013 – REVISED APRIL 2016 www.ti.com Product Folder Links: SN74AUP1T34-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated 11 Layout 11.1 Layout Guidelines To ensure reliability of the device, TI recommends following common printed-circuit board layout guidelines. • Bypass capacitors must be used on power supplies. • Short trace lengths must be used to avoid excessive loading. • Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of signals depending on the system requirements. 11.2 Layout Example Figure 6. Example Layout |
类似零件编号 - SN74AUP1T34QDCKRQ1 |
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类似说明 - SN74AUP1T34QDCKRQ1 |
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