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SN74AUP1G80DSFR 数据表(PDF) 2 Page - Texas Instruments

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部件名 SN74AUP1G80DSFR
功能描述  LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

SN74AUP1G80DSFR 数据表(HTML) 2 Page - Texas Instruments

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AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(
µA)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time − ns
† AUP1G08 data at C
L = 15 pF
Output
Input
Switching Characteristics
at 25 MHz
D
CLK
Q
CLK
D
Q
SN74AUP1G80
SCES593E – JULY 2004 – REVISED MAY 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE PART
TOP-SIDE
TA
PACKAGE(2)
NUMBER
MARKING(3)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP1G80YFPR
_ _ _HX_
0.23-mm Large Bump – YFP
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP1G80YZPR
_ _ _HX_
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY
Reel of 5000
SN74AUP1G80DRYR
HX
–40°C to 85°C
uQFN – DSF
Reel of 5000
SN74AUP1G80DSFR
HX
Reel of 3000
SN74AUP1G80DBVR
SOT (SOT-23) – DBV
H80_
Reel of 250
SN74AUP1G80DBVT
Reel of 3000
SN74AUP1G80DCKR
SOT (SC-70) – DCK
HX_
Reel of 250
SN74AUP1G80DCKT
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLK
D
H
L
L
H
L or H
X
Q 0
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G80


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