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SN74ALVCH16823DGGR 数据表(PDF) 6 Page - Texas Instruments |
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SN74ALVCH16823DGGR 数据表(HTML) 6 Page - Texas Instruments |
6 / 20 page www.ti.com Timing Requirements Switching Characteristics Switching Characteristics SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038F – JULY 1995 – REVISED APRIL 2005 over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.7 V ± 0.2 V ± 0.3 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX fclock Clock frequency (1) 150 150 150 MHz CLR low (1) 3.3 3.3 3.3 tw Pulse duration ns CLK high or low (1) 3.3 3.3 3.3 CLR inactive (1) 0.7 0.7 0.8 Data low before CLK ↑ (1) 1.6 1.6 1.3 tsu Setup time ns Daa high before CLK ↑ (1) 1.1 1.1 1 CLKEN low before CLK ↑ (1) 1.9 1.9 1.5 Data low after CLK ↑ (1) 0.5 0.5 0.5 th Hold time Data high after CLK ↑ (1) 0.1 0.1 0.8 ns CLKEN low after CLK ↑ (1) 0.3 0.3 0.4 (1) This information was not available at the time of publication. over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.7 V FROM TO ± 0.2 V ± 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN TYP MIN MAX MIN MAX MIN MAX fmax (1) 150 150 150 MHz CLK (1) 1 5.8 5.2 1 4.5 tpd Q ns CLR (1) 1 5.4 5.2 1.2 4.6 ten OE Q (1) 1 6 5.7 1 4.8 ns tdis OE Q (1) 1.1 5.4 4.7 1.3 4.5 ns (1) This information was not available at the time of publication. over recommended operating free-air temperature range (unless otherwise noted), V CC = 3.3 ± 0.3 V, CL = 30 pF, RL = 500 Ω VCC = 3.3 V ± 0.3 V FROM TO PARAMETER UNIT (INPUT) (OUTPUT) MIN MAX fmax(1) 250 MHz CLK 1 3.5 tpd Q ns CLR 1.2 4.1 ten OE Q 1 3.8 ns tdis OE Q 1.3 4.5 ns tsk(o)(1) 0.5 ns (1) Values are characterized but not production tested. 6 |
类似零件编号 - SN74ALVCH16823DGGR |
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类似说明 - SN74ALVCH16823DGGR |
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