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SN74ACT2229 数据表(PDF) 4 Page - Texas Instruments |
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SN74ACT2229 数据表(HTML) 4 Page - Texas Instruments |
4 / 18 page SN74ACT2227, SN74ACT2229 DUAL 64 × 1, DUAL 256 × 1 FIRST-IN, FIRST-OUT MEMORIES SCAS220C – JUNE 1992 – REVISED OCTOBER 1997 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION 1AF/AE 2AF/AE 2 16 O Almost-full/almost-empty flag. AF/AE is high when the memory is eight locations or fewer from a full or empty state. AF/AE is set high after reset. 1D 2D 6 20 I Data input GND 7, 8 Ground 1HF 2HF 1 15 O Half-full flag. HF is high when the number of bits stored in memory is greater than or equal to half the FIFO depth. HF is set low after reset. 1IR 2IR 5 19 O Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full and writes are disabled. IR is set low during reset and is set high on the second low-to-high transition of WRTCLK after reset. 1OE 2OE 28 14 I Output enable. The data output of a FIFO is active when OE is high and in the high-impedance state when OE is low. 1OR 2OR 25 11 O Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty and reads are disabled. Ready data is present on the data output when OR is high. OR is set low during reset and set high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory. 1Q 2Q 24 10 O Data outputs. After the first valid write to empty memory, the first bit is output on the third rising edge of RDCLK. OR for the FIFO is asserted high to indicate ready data. 1RDCLK 2RDCLK 27 13 I Read clock. RDCLK is a continuous clock and can be independent of any other clock on the device. A low-to-high transition of RDCLK reads data from memory when the FIFO RDEN and OR are high. OR is synchronous with the low-to-high transition of RDCLK. 1RDEN 2RDEN 26 12 I Read enable. When the RDEN and OR of a FIFO are high, data is read from the FIFO on the low-to-high transition of RDCLK. 1RESET 2RESET 9 23 I Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. Before it is used, a FIFO must be reset after power up. VCC 21, 22 Supply voltage 1WRTCLK 2WRTCLK 3 17 I Write clock. WRTCLK is a continuous clock and can be independent of any other clock on the device. A low-to-high transition of WRTCLK writes data to memory when WRTEN and IR are high. IR is synchronous with the low-to-high transition of WRTCLK. 1WRTEN 2WRTEN 4 18 I Write enable. When WRTEN and IR are high, data is written to the FIFO on a low-to-high transition of WRTCLK. |
类似零件编号 - SN74ACT2229 |
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类似说明 - SN74ACT2229 |
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