Si91841/3

Vishay Siliconix

Document Number: 71447

S-40592—Rev. C, 29-Mar-04

www.vishay.com

9

BLOCK DIAGRAM

Si91841/3

Reference

−

+

Thermal

Sensor

Shutdown

Control

GND

Reverse Polarity

Protection

Current

Limit

SD

BP

Si91841

Only

DETAILED DESCRIPTION

The Si91841/3 is a low-noise, low drop-out and low quiescent

current linear voltage regulator, packaged in a small footprint

Thin SOT23-5 package. The Si91841/3 can supply loads up

to 300 mA. As shown in the block diagram, the circuit consists

of a bandgap reference error, amplifier, p-channel pass

transistor and feedback resistor string. An external bypass

capacitor connected to the BP pin reduces noise at the output.

Additional blocks, not shown in the block diagram, include a

precise current limiter, reverse battery and current protection

and thermal sensor.

Thermal Overload Protection

The thermal overload protection limits the total power

dissipation and protects the device from being damaged.

When the junction temperature exceeds 150_, the device

turns the p-channel pass transistor off.

Reverse Battery Protection

The Si91841/3 has a battery reverse protection circuitry that

GND voltage. There is no current drawn in such an event.

pin is allowed when reverse battery protection is not desired.

Noise Reduction

An external 10-nF bypass capacitor at BP is used to create a

low pass filter for noise reduction. The start-up time is fast,

since a power-on circuit pre-charges the bypass capacitor.

After the power-up sequence the pre-charge circuit is switched

to standby mode in order to save current. It is therefore not

recommended to use larger bypass capacitor values than

50 nF. When the circuit is used without a capacitor, stable

operation is guaranteed.

Auto-Discharge/No-Discharge

path to ground when the SD pin is low. The Si91843 does not

have a discharge path when the SD pin is low.

Stability

The circuit is stable with only a small output capacitor equal to

6 nF/mA (= 1 mF @ 150 mA). Since the bandwidth of the error

amplifier is around 1−3 MHz and the dominant pole is at the

output node, the capacitor should be capacitive in this range,

i.e., for 150-mA load current, an ESR <0.4 W is necessary.

Parasitic inductance of about 10 nH can be tolerated.