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74F632VC 数据表(PDF) 4 Page - National Semiconductor (TI) |
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74F632VC 数据表(HTML) 4 Page - National Semiconductor (TI) |
4 / 14 page Functional Description (Continued) TABLE II Parity Algorithm Check Word 32-Bit Data Word Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CB0 XX XX XX X X X X X X X X X X CB1 XXXXXX X X XX X X X X X X CB2 X X X X XX XX X X X X X X X X CB3 XXX X XX XX XXX X X X X X CB4 XX XXXXXX X X X X X X X X CB5 XXXXXXXX XXXXXX X X CB6 XXXXXXXX X X X X X X X X The seven check bits are parity bits derived from the matrix of data bits as indicated by X for each bit TABLE III Error Function Total Number of Errors Error Flags Data Correction 32-Bit Data Word 7-Bit Check Word ERR MERR 0 0 H H Not Applicable 1 0 L H Correction 0 1 L H Correction 1 1 L L Interrupt 2 0 L L Interrupt 0 2 L L Interrupt H e HIGH Voltage Level L e LOW Voltage Level If the parity of one or more of the check groups is incorrect an error has occurred and the proper error flag or flags will be set LOW Any single error in the 32-bit data word will change the state of either three or five bits of the 7-bit check word Any single error in the 7-bit check word chang- es the state of only that one bit In either case the single error flag (ERR) will be set LOW while the dual error flag (MERR) will remain HIGH Any 2-bit error will change the state of an even number of check bits The 2-bit error is not correctable since the parity tree can only identify single-bit errors Both error flags are set LOW when any 2-bit error is detected Three or more simultaneous bit errors can cause the EDAC to believe that no error a correctable error or an uncorrect- able error has occurred and will produce erroneous results in all three cases It should be noted that the gross-error conditions of all LOWs and all HIGHs will be detected As the corrected word is made available on the data IO port (DB0 through DB31) the check word IO port (CB0 through CB6) presents a 7-bit syndrome error code This syndrome error code can be used to locate the bad memory chip See Table V for syndrome decoding READ-MODIFY-WRITE (BYTE CONTROL) OPERATIONS The ’F632 device is capable of byte-write operations The 39-bit word from memory must first be latched into the Data Bit and Check Bit input latches This is easily accomplished by switching from the read and flag mode (S1 e H S0 e L) to the latch input mode (S1 e H S0 e H) The EDAC will then make any corrections if necessary to the data word and place it at the input of the output data latch This data word must then be latched into the output data latch by taking LEDBO from a LOW to a HIGH Byte control can now be employed on the data word through the OEB0 through OEB3 controls OEB0 controls DB0–DB7 (byte 0) OEB1 controls DB8–DB15 (byte 1) OEB2 controls DB16–DB23 (byte 2) and OEB3 controls DB24–DB31 (byte 3) Placing a HIGH on the byte control will disable the output and the user can modify the byte If a LOW is placed on the byte control then the original byte is allowed to pass onto the data bus unchanged If the original data word is altered through byte control a new check word must be generated before it is written back into memory This is easily accomplished by taking controls S1 and S0 LOW Table VI lists the read-modify-write functions DIAGNOSTIC OPERATIONS The ’F632 is capable of diagnostics that allow the user to determine whether the EDAC or the memory is failing The diagnostic function tables will help the user to see the possi- bilities for diagnostic control In the diagnostic mode (S1 e L S0 e H) the check word is latched into the input latch while the data input latch remains transparent This lets the user apply various data words against a fixed known check word If the user applies a diagnostic data word with an error in any bit location the ERR flag should be LOW If a diagnostic data word with two errors in any bit location is applied the MERR flag should be LOW After the check word is latched into the input latch it can be verified by taking OECB LOW This outputs the latched check word The diagnostic data word can be latched into the output data latch and verified By changing from the diagnostic mode (S1 e L S0 e H) to the correction mode (S1 e H S0 e H) the user can verify that the EDAC will correct the diagnostic data word Also the syndrome bits can be pro- duced to verify that the EDAC pinpoints the error location Table VII lists the diagnostic functions 4 |
类似零件编号 - 74F632VC |
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类似说明 - 74F632VC |
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