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DS92LV1023

SNLS049D – MAY 2000 – REVISED APRIL 2013

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potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming

active until the potential “false lock” pattern changes. The false lock detect circuitry expects the data will

eventually change, causing the Deserializer to lose lock to the data pattern and then continue searching for clock

bits in the serial data stream. Graphical representations of RMT are shown in Figure 3. Please note that RMT

only applies to bits DIN0-DIN8.

Powerdown

When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the

Powerdown state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown

when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In

Powerdown, the PLL stops and the outputs enter TRI-STATE, which disables load current and reduces supply

current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high.

Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the

devices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and

assert LOCK high until lock to the Bus LVDS clock occurs.

TRI-STATE

The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and

DO

−) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other

control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).

When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins

(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the

PLL.

DIN0 Held Low-DIN1 Held High Creates an RMT Pattern

DIN4 Held Low-DIN5 Held High Creates an RMT Pattern

DIN8 Held Low-DIN9 Held High Creates an RMT Pattern

Figure 3. RMT Patterns Seen on the Bus LVDS Serial Output

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

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