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DS90UB902Q-Q1 数据表(PDF) 23 Page - Texas Instruments |
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DS90UB902Q-Q1 数据表(HTML) 23 Page - Texas Instruments |
23 / 50 page DS90UB901Q, DS90UB902Q www.ti.com SNLS322E – JUNE 2010 – REVISED APRIL 2013 Table 2. DS90UB902Q Control Registers (continued) Addr Name Bits Field R/W Default Description (Hex) 7:3 RESERVED 00010'b Reserved 1: Configured as GPIO 2 GPIO0 SET RW 1 0: Configured as ROUT data (OSS_SEL controlled) 1D GPIO[0] Config 0: Output 1 GPIO0 DIR 1 1: Input 0: TRI-STATE 0 GPIO0 EN RW 1 1: Enabled 7:3 RESERVED 0x00'h Reserved 1: Configured as GPIO 2 GPIO1 SET RW 1 0: Configured as ROUT data (OSS_SEL controlled) 1E GPIO[1] Config 0: Output 1 GPIO1 DIR RW 1 1: Input 0: TRI-STATE 0 GPIO1 EN RW 1 1: Enabled 7:3 RESERVED 0x00'h Reserved 1: Configured as GPIO 2 GPIO2 SET RW 0 0: Configured as ROUT0 data (OSS_SEL controlled) 1F GPIO[2] Config 0: Output 1 GPIO2 DIR RW 0 1: Input 0: TRI-STATE 0 GPIO2 EN RW 1 1: Enabled 7:3 RESERVED 0x00'h Reserved 1: Configured as GPIO 2 GPIO3 SET RW 0 0: Configured as ROUT1 data (OSS_SEL controlled) 20 GPIO[3] Config 0: Output 1 GPIO3 DIR RW 0 1: Input 0: TRI-STATE 0 GPIO3 EN RW 1 1: Enabled 7:3 RESERVED 0x00'h Reserved 1: Configured as GPIO 2 GPIO4 SET RW 0 0: Configured as ROUT2 data (OSS_SEL controlled) 21 GPIO[4] Config 0: Output 1 GPIO4 DIR RW 0 1: Input 0: TRI-STATE 0 GPIO4 EN RW 1 1: Enabled 7:3 RESERVED 0x00'h Reserved 1: Configured as GPIO 2 GPIO5 SET RW 0 0: Configured as ROUT3 data (OSS_SEL controlled) 22 GPIO[5] Config 0: Output 1 GPIO5 DIR RW 0 1: Input 0: TRI-STATE 0 GPIO5 EN RW 1 1: Enabled GPCR[7] 0: LOW GPCR[6] 1: HIGH GPCR[5] General Purpose GPCR[4] 23 7:0 RW 0x00'h Control Reg GPCR[3] GPCR[2] GPCR[1] GPCR[0] BIST Enable 24 BIST 0 BIST_EN RW 0 0: Normal operation 1: Bist Enable 25 BIST_ERR 7:0 BIST_ERR R 0x00'h Bist Error Counter Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: DS90UB901Q DS90UB902Q |
类似零件编号 - DS90UB902Q-Q1 |
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类似说明 - DS90UB902Q-Q1 |
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