DS90LV028AQ, DS90LV028AQ-Q1

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SNLS299E – MAY 2008 – REVISED APRIL 2013

DS90LV028AQ Automotive LVDS Dual Differential Line Receiver

Check for Samples: DS90LV028AQ, DS90LV028AQ-Q1

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FEATURES

DESCRIPTION

The DS90LV028AQ is a dual CMOS differential line

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AECQ-100 Grade 1

receiver designed for applications requiring ultra low

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-40°C to +125°C Operating Temperature Range

power dissipation, low noise and high data rates. The

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>400 Mbps (200 MHz) Switching Rates

device is designed to support data rates in excess of

400 Mbps (200 MHz) utilizing Low Voltage Differential

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50 ps Differential Skew (Typical)

Signaling (LVDS) technology.

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0.1 ns Channel-to-Channel Skew (Typical)

The DS90LV028AQ accepts low voltage (350 mV

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2.5 ns Maximum Propagation Delay

typical) differential input signals and translates them

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3.3V Power Supply Design

to 3V CMOS output levels. The DS90LV028AQ has a

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Flow-Through Pinout

flow-through design for easy PCB layout.

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Power Down High Impedance on LVDS Inputs

The DS90LV028AQ and companion LVDS line driver

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Low Power design (18mW @ 3.3V static)

DS90LV027AQ provide a new alternative to high

power PECL/ECL devices for high speed point-to-

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LVDS Inputs Accept LVDS/CML/LVPECL

point interface applications.

Signals

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Conforms to ANSI/TIA/EIA-644 Standard

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Available in SOIC Package

Connection Diagram

Figure 1. SOIC

See Package Number D0008A

Functional Diagram

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