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ADF4107BCP 数据表(PDF) 6 Page - Analog Devices

部件名 ADF4107BCP
功能描述  PLL Frequency Synthesizer
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADF4107BCP 数据表(HTML) 6 Page - Analog Devices

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ADF4107
Rev. 0 | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
RSET
CP
CPGND
AGND
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RFINB
RFINA
AVDD
REFIN
VP
DVDD
ADF4107
TOP VIEW
(Not to Scale)
TSSOP
Figure 3. ADF4107 TSSOP (Top View)
15 MUXOUT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
11 CE
4
5
RFINB
RFINA
PIN 1
INDICATOR
TOP VIEW
ADF4107
CSP
(Chip Scale Package)
Figure 4. ADF4107 Chip Scale Package
Table 4. Pin Functional Descriptions
Mnemonic
Function
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage
potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAX
CP
R
I
5
.
25
=
so, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
CP
Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO.
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
AGND
Analog Ground. This is the ground return path of the prescaler.
RFINB
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor,
typically 100 pF. See Figure 18.
RFINA
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
AVDD
Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. AVDD must be the same value as DVDD.
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See
Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
DGND
Digital Ground.
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking
the pin high will power up the device, depending on the status of the power-down bit, F2.
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift
register on the CLK rising edge. This input is a high impedance CMOS input.
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance
CMOS input.
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the
latch being selected using the control bits.
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed
externally.
DVDD
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed
as close as possible to this pin. DVDD must be the same value as AVDD.
VP
Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5
V and used to drive a VCO with a tuning range of up to 5 V.


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