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DP83901 数据表(PDF) 29 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 DP83901
功能描述  Serial Network Interface Controller
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

DP83901 数据表(HTML) 29 Page - National Semiconductor (TI)

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100 Internal Registers (Continued)
103 REGISTER DESCRIPTIONS
(Continued)
RECEIVE STATUS REGISTER (RSR)
0CH (READ)
This register records status of the received packet including information on errors and the type of address match either
physical or multicast The contents of this register are written to buffer memory by the DMA after reception of a good packet If
packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous
packet is received If packets with errors are to be rejected the RSR will not be written to memory The contents will be cleared
when the next packet arrives CRC errors Frame Alignment errors and missed packets are counted internally by the SNIC which
relinguishes the Host from reading the RSR in real time to record errors for Network Management Functions The contents of
this register are not specified until after the first reception
76543210
DFR
DIS
PHY
MPA
FO
FAE
CRC
PRX
Bit
Symbol
Description
D0
PRX
Packet Received Intact
Indicates packet received without error (Bits CRC FAE FO and MPA
are zero for the received packet)
D1
CRC
CRC Error
Indicates packet received with CRC error Increments Tally Counter (CNTR1) This
bit will also be set for Frame Alignment errors
D2
FAE
Frame Alignment Error
Indicates that the incoming packet did not end on a byte boundary and
the CRC did not match at last byte boundary Increments Tally Counter (CNTR0)
D3
FO
FIFO Overrun
This bit is set when the FIFO is not serviced causing overflow during reception
Reception of the packet will be aborted
D4
MPA
Missed Packet
Set when a packet intended for node cannot be accepted by SNIC because of a
lack of receive buffers or if the controller is in monitor mode and did not buffer the packet to
memory Increments Tally Counter (CNTR2)
D5
PHY
PhysicalMulticast Address
Indicates whether received packet had a physical or multicast
address type
0 Physical Address Match
1 MulticastBroadcast Address Match
D6
DIS
Receiver Disabled
Set when receiver disabled by entering Monitor mode Reset when receiver
is re-enabled when exiting Monitor mode
D7
DFR
Deferring
Set when internal Carrier Sense or Collision signals are generated in the ENDEC
module If the transceiver has asserted the CD line as a result of the jabber this bit will stay set
indicating the jabber condition
Note
Following coding applies to CRC and FAE bits
FAE
CRC
Type of Error
0
0
No Error (Good CRC and k6 Dribble Bits)
0
1
CRC Error
1
0
Illegal Will Not Occur
1
1
Frame Alignment Error and CRC Error
29


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