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DP83902A 数据表(PDF) 64 Page - National Semiconductor (TI) |
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DP83902A 数据表(HTML) 64 Page - National Semiconductor (TI) |
64 / 70 page 150 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary (Continued) Remote DMA (Write Cycle) Recovery Time TLF11157 – 45 Symbol Parameter Min Max Units bprqh Bus Clock to Port Request High (Note 1) 42 ns wprql WACK to Port Request Low 50 ns wackw WACK Pulse Width 25 ns bprdl Bus Clock to Port Read Low (Note 2) 55 ns bprdh Bus Clock to Port Read High 40 ns wprq Remote Write Port Request to Port 12 BSCK Request Time (Notes 3 4 5) Note 1 The first port request is issued in response to the remote write command It is subsequently issued on T1 clock cycles following completion of remote DMA cycles Note 2 The start of the remote DMA write following WACK is dependent on where WACK is issued relative to BSCK and whether a local DMA is pending Note 3 Assuming wackw k 1 BSCK and no local DMA interleave no CS immediate BACK and WACK goes high before T4 Note 4 WACK must be high for a minimum of 7 BSCK Note 5 This is not a measured value but guaranteed by design Reset Timing TLF11157 – 64 Symbol Parameter Min Max Units rstw Reset Pulse Width (Note 1) 8 BSCK Cycles or TXC Cycles (Note 2) Note 1 The RESET pulse requires that BSCK and TXC be stable On power up RESET should not be raised until BSCK and TXC have become stable Several registers are affected by RESET Consult the register descriptions for details Note 2 The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low If BSCK k TXC then RESET e 8 c BSCK If TXC k BSCK then RESET e 8 c TXC 64 |
类似零件编号 - DP83902A |
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类似说明 - DP83902A |
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