DP83902A datasheet(38/70 Pages) NSC

部件名	DP83902A

功能描述	ST-NICTM Serial Network Interface Controller for Twisted Pair

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制造商	NSC [National Semiconductor (TI)]

网页	http://www.national.com

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120 Loopback Diagnostics (Continued)

To initiate a loopback the user first assembles the loopback

packet then selects the type of loopback using the Transmit

Configuration register bits LB0 LB1 The transmit configura-

tion register must also be set to enable or disable CRC gen-

eration during transmission The user then issues a normal

transmit command to send the packet During loopback the

receiver checks for an address match and if CRC bit in the

TCR is set the receiver will also check the CRC The last 8

bytes of the loopback packet are buffered and can read out

of the FIFO using the FIFO read port

Loopback Modes

MODE 1

Loopback through the NIC Module (LB1 e 0

LB0 e 1) If this loopback is used the NIC Modules’s serial-

izer is connected to the deserializer

MODE 2

Loopback through the ENDEC Module (LB1 e 1

LB0 e 0) If the loopback is to be performed through the

SNI the ST-NIC provides a control (LPBK) that forces the

ENDEC module to loopback all signals

MODE 3

Loopback to cable (LB1 e 1 LB0 e 1) Packets

can be transmitted to the cable in loopback mode to check

all of the transmit and receive paths and the cable itself

Note

Collision and Carrier Sense can be generated by the ENDEC module

and are masked by the NIC module It is not possible to go directly

between the loopback modes it is necessary to return to normal oper-

ation (00H) when changing modes

Reading the Loopback Packet

The last 8 bytes of a received packet can be examined by 8

consecutive reads of the FIFO register The FIFO pointer is

incremented after the rising edge of the CPU’s read strobe

by internally synchronizing and advancing the pointer This

may take up to four bus clock cycles if the pointer has not

been incremented by the time the CPU reads the FIFO reg-

ister again the ST-NIC will insert wait states

Note

The FIFO may only be read during Loopback Reading the FIFO at

any other time will cause the ST-NIC to malfunction

Alignment of the Received Packet in the FIFO

Reception of the packet in the FIFO begins at location zero

after the FIFO pointer reaches the last location in the FIFO

the pointer wraps to the top of the FIFO overwriting the

previously received data This process is continued until the

last byte is received The ST-NIC then appends the received

byte count in the next two locations of the FIFO The con-

tents of the Upper Byte Count are also copied to the next

FIFO location The number of bytes used in the loopback

packet determines the alignment of the packet in the FIFO

The alignment for a 64-byte packet is shown below

FIFO

Location

Contents

0

Lower Byte Count

First Byte Read

1

Upper Byte Count

Second Byte Read

2

Upper Byte Count

3

Last Byte

4

CRC1

5

CRC2

6

CRC3

7

CRC4

Last Byte Read

For the following alignment in the FIFO the packet length

should be (N x 8) a 5 Bytes Note that if the CRC bit in the

TCR is set CRC will not be appended by the transmitter If

the CRC is appended by the transmitter the 1st four bytes

bytes N-3 to N correspond to the CRC

FIFO

Location

Contents

0

Byte N-4

First Byte Read

1

Byte N-3 (CRC1)

Second Byte Read

2

Byte N-2 (CRC2)

3

Byte N-1 (CRC3)

4

Byte N (CRC4)

5

Lower Byte Count

6

Upper Byte Count

Last Byte Read

7

Upper Byte Count

LOOPBACK TESTS

Loopback capabilities are provided to allow certain tests to

be performed to validate operation of the DP83902A ST-

NIC prior to transmitting and receiving packets on a live

network Typically these tests may be performed during

power up of a node The diagnostic provides support to veri-

fy the following

1 Verify integrity of data path Received data is checked

against transmitted data

2 Verify the CRC logic’s capability to generate good CRC

on transmit verify CRC on receive (good or bad CRC)

38

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