Preliminary Technical Data

AD9289

Rev. PrJ | Page 7 of 16

6/25/2004

DEFINITIONS

ANALOG BANDWIDTH

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

APERTURE DELAY

The delay between the 50% point of the rising edge of the

ENCODE command and the instant at which the analog input is

sampled.

APERTURE UNCERTAINTY (JITTER)

The sample -to-sample variation in aperture delay.

CROSSTALK

Coupling onto one channel being driven by a low level (-40 dBFS)

signal when the adjacent interfering channel is driven by a full-

scale signal.

DIFFERENTIAL ANALOG INPUT RESISTANCE,

DIFFERENTIAL ANALOG INPUT CAPACITANCE,

AND DIFFERENTIAL ANALOG INPUT IMPEDANCE

The real and complex impedances measured at each analog input

port. The resistance is measured statically and the capacitance and

differential input impedances are measured with a network

analyzer.

DIFFERENTIAL ANALOG INPUT VOLTAGE RANGE

The peak to peak differential voltage that must be applied to the

converter to generate a full scale response. Peak differential

voltage is computed by observing the voltage on a single pin and

subtracting the voltage from the other pin, which is 180 degrees

out of phase. Peak to peak differential is computed by rotating the

inputs phase 180 degrees and taking the peak measurement again.

Then the difference is computed between both peak measurements.

DIFFERENTIAL NONLINEARITY

The deviation of any code width from an ideal 1 LSB step.

EFFECTIVE NUMBER OF BITS

The effective number of bits (ENOB) is calculated from the

measured SNR based on the equation:

02

.

6

76

.

1

dB

SNR

ENOB

=

CLOCK PULSE WIDTH/DUTY CYCLE

Pulse width high is the minimum amount of time that the Clock

pulse (CLK+) should be left in logic “1” state to achieve rated

performance; pulse width low is the minimum time the clock pulse

in text. At a given clock rate, these specs define an acceptable

clock duty cycle.

FULL SCALE INPUT POWER

Expressed in dBm. Computed using the following equation:





























=

001

.

log

10

2

Input

Fullscale

Fullscale

Z

V

Power

rms

GAIN ERROR

Gain error is the difference between the measured and ideal full

scale input voltage range of the worst ADC.

GAIN MATCHING

Expressed in %FSR. Computed using the following equation:

%

100

*

2

min

max

min

max













+

−

=

FSR

FSR

FSR

FSR

ng

GainMatchi

HARMONIC DISTORTION, SECOND

The ratio of the rms signal amplitude to the rms value of the

second harmonic component, reported in dBc.

HARMONIC DISTORTION, THIRD

The ratio of the rms signal amplitude to the rms value of the third

harmonic component, reported in dBc.

INTEGRAL NONLINEARITY

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a “best straight line”

determined by a least square curve fit.

MINIMUM CONVERSION RATE

The encode rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed limit.