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AD8328ARQ-REEL 数据表(PDF) 7 Page - Analog Devices

部件名 AD8328ARQ-REEL
功能描述  5 V Upstream Cable Line Driver
Download  16 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8328ARQ-REEL 数据表(HTML) 7 Page - Analog Devices

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REV. 0
AD8328
–7–
VIN+
VIN–
VCC
GND
AD8328
BYP
RL
5V
1
2
1
2
VIN
VIN
VOUT+
VOUT–
Figure 4. Characterization Circuit
APPLICATIONS
General Applications
The AD8328 is primarily intended for use as the power amplifier
(PA) in DOCSIS (Data Over Cable Service Interface Specification)
certified cable modems and CATV set-top boxes. The upstream
signal is either a QPSK or QAM signal generated by a DSP, a
dedicated QPSK/QAM modulator, or a DAC. In all cases, the
signal must be low-pass filtered before being applied to the PA in
order to filter out-of-band noise and higher order harmonics from
the amplified signal.
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the output
power by applying gain or attenuation. The ability to vary the
output power of the AD8328 ensures that the signal from the cable
modem will have the proper level once it arrives at the head-end.
The upstream signal path commonly includes a diplexer and cable
splitters. The AD8328 has been designed to overcome losses asso-
ciated with these passive components in the upstream cable path.
Circuit Description
The AD8328 is composed of three analog functions in the power-up
or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differential
configuration, it is imperative that the input signals be 180 degrees out
of phase and of equal amplitude. A vernier is used in the input
stage for controlling the fine 1 dB gain steps. This stage then drives
a DAC, which provides the bulk of the AD8328’s attenuation. The
signals in the preamp and DAC gain blocks are differential to
improve the PSRR and linearity. A differential current is fed from
the DAC into the output stage. The output stage maintains 300
differential output impedance, which maintains proper match to 75
when used with a 2:1 balun transformer.
SPI Programming and Gain Adjustment
The AD8328 is controlled through a serial peripheral interface
(SPI) of three digital data lines: CLK,
DATEN, and SDATA.
Changing the gain requires eight bits of data to be streamed into
the SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the
DATEN pin, which activates the
CLK line. With the CLK line activated, data on the SDATA line
is clocked into the serial shift register on the rising edge of the
CLK pulses, most significant bit (MSB) first. The 8-bit data-word
is latched into the attenuator core on the rising edge of the
DATEN line. This provides control over the changes in the
output signal level. The serial interface timing for the AD8328
is shown in Figures 2 and 3. The programmable gain range of
the AD8328 is –28 dB to +31 dB with steps of 1 dB per least
significant bit (LSB). This provides a total gain range of 59 dB.
The AD8328 was characterized with a differential signal on the
input and a TOKO 458PT-1087 2:1 transformer on the output.
The AD8328 incorporates supply current scaling with gain code,
as seen in TPC 12. This allows reduced power consumption when
operating in lower gain codes.
Input Bias, Impedance, and Termination
The VIN+ and VIN– inputs have a dc bias level of VCC/2; therefore
the input signal should be ac-coupled as seen in the typical
application circuit (see Figure 5). The differential input impedance
of the AD8328 is approximately 1.6 k
Ω, while the single-ended
input is 800
Ω. The high input impedance of the AD8328 allows
flexibility in termination and properly matching filter networks.
The AD8328 will exhibit optimum performance when driven
with a pure differential signal.
Output Bias, Impedance, and Termination
The output stage of the AD8328 requires a bias of +5 V. The
+5 V power supply should be connected to the center tap of the
output transformer. Also, the VCC that is being applied to the
center tap of the transformer should be decoupled as seen in the
typical applications circuit (Figure 5).
DATEN
SDATA
CLK
VCC
SLEEP
NC
GND
VCC
VIN–
VIN+
BYP
AD8328
QSOP
TXEN
0.1 F
10 F
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SLEEP
GND
GND
GND
GND
TXEN
RAMP
VOUT–
VOUT+
GND
TO DIPLEXER
ZIN = 75
TOKO 458PT-1087
1k
1k
1k
1k
1k
DATEN
SDATA
CLK
VIN+
VIN–
165
ZIN = 150
0.1 F
0.1 F
0.1 F
0.1 F
Figure 5. Typical Application Circuit


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