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DP83901A 数据表(PDF) 20 Page - National Semiconductor (TI) |
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DP83901A 数据表(HTML) 20 Page - National Semiconductor (TI) |
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20 / 62 page  100 Internal Registers All registers are 8-bit wide and mapped into four pages which are selected in the Command Register (PS0 PS1) Pins RA0 – RA3 are used to address registers within each page Page 0 registers are those registers which are com- monly accessed during SNIC operation while page 1 regis- ters are used primarily for initialization The registers are partitioned to avoid having to perform two writeread cycles to access commonly used registers 101 REGISTER ADDRESS MAPPING TLF10469 – 16 102 REGISTER ADDRESS ASSIGNMENTS Page 0 Address Assignments (PS1 e 0 PS0 e 0) RA0 – RA3 RD WR 00H Command (CR) Command (CR) 01H Current Local DMA Page Start Register Address 0 (CLDA0) (PSTART) 02H Current Local DMA Page Stop Register Address 1 (CLDA1) (PSTOP) 03H Boundary Pointer Boundary Pointer (BNRY) (BNRY) 04H Transmit Status Transmit Page Start Register (TSR) Address (TPSR) 05H Number of Collisions Transmit Byte Count Register (NCR) Register 0 (TBCR0) 06H FIFO (FIFO) Transmit Byte Count Register 1 (TBCR1) 07H Interrupt Status Interrupt Status Register (ISR) Register (ISR) 08H Current Remote DMA Remote Start Address Address 0 (CRDA0) Register 0 (RSAR0) RA0 – RA3 RD WR 09H Current Remote DMA Remote Start Address Address 1 (CRDA1) Register 1 (RSAR1) 0AH Reserved Remote Byte Count Register 0 (RBCR0) 0BH Reserved Remote Byte Count Register 1 (RBCR1) 0CH Receive Status Receive Configuration Register (RSR) Register (RCR) 0DH Tally Counter 0 Transmit Configuration (Frame Alignment Register (TCR) Errors) (CNTR0) 0EH Tally Counter 1 Data Configuration (CRC Errors) Register (DCR) (CNTR1) 0FH Tally Counter 2 Interrupt Mask Missed Packet Register (IMR) Errors) (CNTR2) 20 |
类似零件编号 - DP83901A |
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类似说明 - DP83901A |
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