CDCVF2509A

SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED

For application information, see application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking

(SSC) (SCAA039).

The CDCVF2509A is characterized for operation from 0°C to 85°C.

Because it is based on PLL circuitry, the CDCVF2509A requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application of a

fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals.

FUNCTION TABLE

Inputs

Outputs

PLL

AVCC

1G/2G

CLK

1Y/2Y

FBOUT

GND

L

Signal

L

Signal (delayed)

Bypassed / Off

GND

H

Signal

Signal (delayed)

Signal (delayed)

Bypassed / Off

3.3 V (nom)

L

CLK > 1 MHz

L

CLK (in phase)

On

3.3 V (nom)

H

CLK > 1 MHz

CLK (in phase)

CLK (in phase)

On

3.3 V (nom)

X

CLK < 1 MHz

L

L

Off

2

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