数据搜索系统,热门电子元器件搜索 |
|
CDCV857BIDGGRG4 数据表(PDF) 6 Page - Texas Instruments |
|
CDCV857BIDGGRG4 数据表(HTML) 6 Page - Texas Instruments |
6 / 16 page CDCV857B, CDCV857BI 2.5-V PHASE-LOCK LOOP CLOCK DRIVER SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT Without load fO = 170 MHz 100 110 Without load fO = 200 MHz 105 120 Differential outputs t i t d ith fO = 170 MHz 200 240 IDD Dynamic current on VDDQ terminated with 120 Ω/CL = 0 pF fO = 200 MHz 210 250 mA Differential outputs t i t d ith fO = 170 MHz 260 300 terminated with 120 Ω/CL = 14 pF fO = 200 MHz 280 320 ΔC Part-to-part input capacitance variation VDDQ = 2.5 V, VI = VDDQ or GND 1 pF CI(Δ) Input capacitance difference between CLK and CLKB, FBIN, and FBINB VDDQ = 2.5 V, VI = VDDQ or GND 0.25 pF CO Output capacitance VDDQ = 2.5 V, VO = VDDQ or GND 2.5 3 3.5 pF † All typical values are at a respective nominal VDDQ. timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN MAX UNIT f Operating clock frequency 60 200 MHz fCLK Application clock frequency 60 200 MHz Input clock duty cycle 40% 60% Stabilization time{ (PLL mode) 10 μs Stabilization time} (Bypass mode) 30 ns † The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. ‡ A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND). switching characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLHw Low to high level propagation delay time Test mode/CLK to any output 3.5 ns tPHLw High-to low level propagation delay time Test mode/CLK to any output 3.5 ns t W Jitter (period) See Figure 7 66 MHz −60 60 ps tjit(per)W Jitter (period), See Figure 7 100/133/167/200 MHz −35 35 ps t W Jitter (cycle to cycle) See Figure 4 66 MHz −75 75 ps tjit(cc)W Jitter (cycle-to-cycle), See Figure 4 100/133/167/200 MHz −50 50 ps t W Half period jitter See Figure 8 66 MHz −100 100 ps tjit(hper)W Half-period jitter, See Figure 8 100/133/167/200 MHz −75 75 ps tslr(o) Output clock slew rate, See Figure 9 Load: 120 Ω/14 pF 1 2 V/ns t Static phase offset See Figure 5 66 MHz –100 100 ps t(Ø) Static phase offset, See Figure 5 100/133/167/200 MHz –50 50 ps tsk(o) Output skew, See Figure 6 Load: 120 Ω/14 pF 70 100 ps tr, tf Output rise and fall times (20% − 80%) Load: 120 Ω/14 pF 600 900 ps § Refers to the transition of the noninverting output. ¶ This parameter is assured by design but can not be 100% production tested. |
类似零件编号 - CDCV857BIDGGRG4 |
|
类似说明 - CDCV857BIDGGRG4 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |