数据搜索系统,热门电子元器件搜索 |
|
AD1980JST 数据表(PDF) 1 Page - Analog Devices |
|
AD1980JST 数据表(HTML) 1 Page - Analog Devices |
1 / 32 page a AD1980 AC ’97 SoundMAX®Codec REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2002 Analog Devices, Inc. All rights reserved. FEATURES AC ’97 2.3 COMPATIBLE FEATURES 6 DAC Channels for 5.1 Surround S/PDIF Output Integrated Stereo Headphone Amplifier Variable Rate Audio Double Rate Audio (fS = 96 kHz) Greater than 90 dB Dynamic Range 20-Bit PCM DACs Line-Level Mono ”Phone” Input High Quality CD Input Selectable MIC Input with Preamp AUX and Line_In Stereo Inputs External Amplifier Power-Down Control Power Management Modes 48-Lead LQFP Package FUNCTIONAL BLOCK DIAGRAM MC1 MC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L G G MIC PREAMP CD DIFF AMP M GA M GA M GA M M M GA M GA M GA M GA M GA M M M M G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z M G 16-BIT - ADC M G 16-BIT - ADC PCM L/R ADC RATE VREF G VREFOUT LINE_IN_R CODEC CORE VOLTAGE REFERENCE DAC SLOT LOGIC AC '97 CONTROL REGISTERS EAPD ANALOG MIXING CONTROL LOGIC PLL XTL_OUT XTL_IN SPDIF SPDIF TX ID0 ID1 RESET SYNC BITCLK SDATA_OUT SDATA_IN JS0 JS1 EAPD AD1980 20-BIT - DAC PCM LFE DAC RATE M G MZ A LFE_OUT MZ A CENTER_OUT 20-BIT - DAC PCM FRONT DAC RATE M G M G M G 20-BIT - DAC M G 20-BIT - DAC M G PCM SURR DAC RATE EQ 20-BIT - DAC EQ 20-BIT - DAC MZ A LINE_OUT_L MZ A MONO_OUT MZ A LINE_OUT_R M A SURR_OUT_L/ HP_OUT_L M A SURR_OUT_R/ HP_OUT_R HP HP ENHANCED FEATURES Integrated Parametric Equalizer Stereo MIC Preamp Support Integrated PLL for System Clocking Variable Sample Rate 7 kHz to 96 kHz Jack Sense (Auto Topology Switching) Software Controlled VREF_OUT for MIC Bias Software Enabled Outputs for Jack Sharing Auto Down-Mix and Channel Spreading Modes |
类似零件编号 - AD1980JST |
|
类似说明 - AD1980JST |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |