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DAC7741 Datasheet(数据表) 15 Page - Texas Instruments

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部件型号  DAC7741
说明  16-Bit, Single Channel DIGITAL-TO-ANALOG CONVERTER With Internal Reference and Parallel Interface
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DAC7741 Datasheet(HTML) 15 Page - Texas Instruments

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 15 page
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DAC7741
15
SBAS248B
www.ti.com
DAC RESET
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a low signal on
RST. Once RST is LOW, the DAC output will begin settling to
the mid-scale or min-scale code depending on the state of the
RSTSEL input. A HIGH value on RSTSEL will cause VOUT to
reset to the mid-scale code (8000H) and a LOW value will reset
VOUT to min-scale (0000H). A change in the state of the
RSTSEL input while RST is LOW will cause a corresponding
change in the reset command selected internally and conse-
quently change the output value of VOUT of the DAC. Note that
a valid reset signal also resets the input register of the DAC to
the value specified by the state of RSTSEL.
GAIN AND OFFSET CALIBRATION
The architecture of the DAC7741 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7741
has built-in feedback resistors and output amplifier summing
points brought out of the package in order to make the
absolute calibration possible. Figures 5 and 6 illustrate the
relationship of offset and gain adjustments for the DAC7741
in a unipolar configuration and in a bipolar configuration,
respectively.
When calibrating the DAC output, offset should be adjusted
first to avoid first order interaction of adjustments. In unipolar
mode, the DAC7741 offset is adjusted from code 0000H and
for either bipolar mode, offset adjustments are made at code
8000H. Gain adjustment can then be made at code FFFFH for
each configuration, where the output of the DAC should be
at +10V for the 0V to +10V – 1LSB or
±10V output range and
+5V – 1LSB for the
±5V output range. Figure 7 shows the
generalized external offset and gain adjustment circuitry
using potentiometers.
Digital Input
H
Input =
FFFF
H
Input =
0000
Gain Adjust
Rotates
the Line
1LSB
+ Full Scale
(+V
REF)
Zero Scale
(AGND)
Offset Adjust Translates the Line
Digital Input
Input =
0000
H
Gain
Adjust
Rotates
the Line
1LSB
+ Full
Scale
– Full-Scale
(–V
REF OR –VREF/2)
Offset
Adjust
Translates
the Line
H
Input =
FFFF
Input = 8000
H
(+V
REF or +VREF/2)
FIGURE 5.
Relationship of Offset and Gain Adjustments for
VOUT = 0V to +10V Output Configuration.
FIGURE 6.
Relationship of Offset and Gain Adjustments
for VOUT = –10V to +10V Output Configuration.
(Same theory applies for VOUT = –5V to +5V).
FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment.
15
16
17
18
Optional Gain
Adjust
(Other Connections Omitted
for Clarity)
REF
OUT
REFADJ
REF
IN
NC
Optional Offset
Adjust
R
POT1
R
S
V
OADJ
+
I
SJ
R
1
R
POT2




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