TLF6551

October 1992

DM54161DM74161DM74163

Synchronous 4-Bit Counters

General Description

These synchronous presettable counters feature an inter-

nal carry look-ahead for application in high-speed counting

designs The 161 and 163 are 4-bit binary counters The

carry output is decoded by means of a NOR gate thus pre-

venting spikes during the normal counting mode of opera-

tion Synchronous operation is provided by having all flip-

flops clocked simultaneously so that the outputs change co-

incident with each other when so instructed by the count-

enable inputs and internal gating This mode of operation

eliminates the output counting spikes which are normally

associated with asynchronous (ripple clock) counters A

buffered clock input triggers the four flip-flops on the rising

(positive-going) edge of the clock input waveform

These counters are fully programmable that is the outputs

may be preset to either level As presetting is synchronous

setting up a low level at the load input disables the counter

and causes the outputs to agree with the setup data after

the next clock pulse regardless of the levels of the enable

input The clear function for the 161 is asynchronous and a

low level at the clear input sets all four of the flip-flop out-

puts low regardless of the levels of clock load or enable

inputs The clear function for the 163 is synchronous and a

low level at the clear input sets all four of the flip-flop out-

puts low after the next clock pulse regardless of the levels

of the enable inputs This synchronous clear allows the

count length to be modified easily as decoding the maxi-

mum count desired can be accomplished with one

external NAND gate The gate output is connected to the

clear input to synchronously clear the counter to all low out-

puts Low-to-high transitions at the clear input of the 163 are

also permissible regardless of the logic levels on the clock

enable or load inputs

The carry look-ahead circuitry provides for cascading coun-

ters for n-bit synchronous applications without additional

gating Instrumental in accomplishing this function are two

count-enable inputs and a ripple carry output Both count-

enable inputs (P and T) must be high to count and input T is

fed forward to enable the ripple carry output The ripple car-

ry output thus enabled will produce a high-level output pulse

with a duration approximately equal to the high-level portion

can be used to enable successive cascaded stages High-

to-low-level transitions at the enable P or T inputs of the 161

through 163 may occur regardless of the logic level on the

clock

Features

Y

Synchronously programmable

Y

Internal look-ahead for fast counting

Y

Carry output for n-bit cascading

Y

Synchronous counting

Y

Load control line

Y

Diode-clamped inputs

Connection Diagram

Dual-In-Line Package

TLF6551 – 1

Order Number DM54161J DM54161W

DM74161N or DM74163N

See NS Package Number J16A N16E or W16A

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A