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DAC60004IDMDT 数据表(PDF) 8 Page - Texas Instruments |
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DAC60004IDMDT 数据表(HTML) 8 Page - Texas Instruments |
8 / 38 page 1 2 32 SCLK SYNC SDIN LDAC 2 LDAC 1 CLR tw3 tsu tw2 tw1 tc td1 tsu1 th1 t19 DB31 DB0 td4 tw5 t19 VOUTX td2 tw4 td3 8 DAC80004, DAC70004, DAC60004 SLASED6B – APRIL 2016 – REVISED JUNE 2016 www.ti.com Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Does not include output settling tiime 7.6 DACx0004 Timing Requirements At TA = -40°C to +125°C, Trise = Tfall = 1 nV/sec (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, SDO pin loaded with 10 pF 4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 4.5 V UNIT MIN TYP MAX MIN TYP MAX SERIAL WRITE and READ tc SCLK cycle time 20 40 ns tw1 SCLK high pulse duration 10 20 ns tw2 SCLK low pulse duration 10 20 ns tsu SYNC to SCLK falling edge setup time 15 30 ns tsu1 Data setup time 5 10 ns th1 Data hold time 5 10 ns td1 SCLK falling edge to SYNC rising edge delay time 5 10 ns tw3 Minimum SYNC high pulse duration(1) 25 35 ns td2 SYNC rising edge to SCLK fall ignore delay time 15 20 ns tw4 LDAC pulse duration low 20 30 ns td3 SCLK falling edge to LDAC rising edge delay time 10 20 ns tw5 CLR minimum pulse duration low 10 20 ns td4 SCLK falling edge to LDAC falling edge delay time 10 20 ns tv SCLK rising edge to SDO valid time 18 18 ns td5 SCLK falling edge to SYNC rising edge delay time 5 10 ns td6 SYNC rising edge to SCLK rising edge delay time 5 10 ns td7 SYNC rising edge to LDAC or CLR falling edge delay time 20 40 ns t19 CLR pulse activation time 20 20 ns t20 Successive DAC Update 2.4 2.4 µs (1) Asynchronous LDAC update (2) Synchronous LDAC update Figure 1. Stand-Alone Timing |
类似零件编号 - DAC60004IDMDT |
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类似说明 - DAC60004IDMDT |
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