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DAC9881SBRGET Datasheet(数据表) 5 Page - Texas Instruments

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部件型号  DAC9881SBRGET
说明  18-Bit, Single-Channel, Low-Noise, Voltage-Output DIGITAL-TO-ANALOG CONVERTER
下载  39 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 

 
 5 page
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ELECTRICAL CHARACTERISTICS: AVDD = 2.7V
DAC9881
www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008
All specifications at TA = TMIN to TMAX, AVDD = +2.7V to +3.3V, IOVDD = +1.8V to AVDD, VREFH = 2.5V, VREFL = 0V and gain =
1X mode, unless otherwise noted.
DAC9881
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY(1)
Measured by line
DAC9881S
±2.5
±3.5
LSB
passing through
Integral linearity error
codes 2048 and
DAC9881SB
±2
±3
LSB
262143
Measured by line
DAC9881S
±1
±2
LSB
passing through
Differential linearity error
codes 2048 and
DAC9881SB
±0.75
±1.5
LSB
262143
TA = +25°C, code = 2048
±32
LSB
Zero-scale error
TMIN to TMAX, code = 2048
±64
LSB
Zero-scale drift(2)
Code = 2048
±0.5
±1.6
ppm/°C of FSR
TA = +25°C, measured by line passing through codes 2048
Gain error
±32
±64
LSB
and 262143
Gain temperature drift(2)
Measured by line passing through codes 2048 and 262143
±0.5
±0.8
ppm/°C
PSRR(2)
VOUT = full-scale, AVDD = +3V ±10%
64
LSB/V
ANALOG OUTPUT(2)
Voltage output(3)
0
AVDD
V
Device operating for 500 hours at +25°C
0.2
ppm of FSR
Output voltage drift vs time
Device operating for 1000 hours at +25°C
0.4
ppm of FSR
Output current(4)
2.5
mA
Maximum load capacitance
200
pF
Short-circuit current
+31/–50
mA
REFERENCE INPUT(2)
VREFH input voltage range
AVDD = +3V
1.25
2.5
AVDD
V
VREFH input capacitance
5
pF
VREFH input impedance
4.5
k
VREFL input voltage range
–0.2
0
+0.2
V
VREFL input capacitance
4.5
pF
VREFL input impedance
5
k
DYNAMIC PERFORMANCE(2)
To ±0.003% FS, RL = 10kΩ, CL = 50pF, code 04000h to
Settling time
5
µs
3C000h
Slew rate
From 10% to 90% of 0V to +2.5V
2.5
V/
µs
VREFH = 2.5V, gain = 1X mode
18
nV-s
Code = 1FFFFh to
Code change glitch
VREFH = 1.25V, gain = 1X mode
9
nV-s
20000h to 1FFFFh
VREFH = 1.25V, gain = 2X mode
10
nV-s
Digital feedthrough
CS = high, fSCLK = 1kHz
1
nV-s
Gain = 1
24
30
nV/
√Hz
f = 1kHz to 100kHz,
Output noise voltage density
full-scale output
Gain = 2
40
48
nV/
√Hz
Output noise voltage
f = 0.1Hz to 10Hz, full-scale output
2
µV
PP
(1)
DAC output range is 0V to +2.5V. 1LSB = 9.5
µV.
(2)
Ensured by design. Not production tested.
(3)
The output from the VOUT pin = [(VREFH – VREFL)/262144] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0V to AVDD.
The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
(4)
Refer to Figure 55, Figure 56, and Figure 57 for details.
Copyright © 2008, Texas Instruments Incorporated
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