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The DAC9881 has a power-on reset function. After power-on, the value of the input register, the DAC latch, and
the output from the VOUT pin are set to the value defined by the RSTSEL pin.
After a power-on reset or a hardware reset, the output voltage from the VOUT pin and the values of the input
register and DAC latch are determined by the status of the RSTSEL pin and the input data format, as shown in
Table 3. Reset Value
VALUE OF INPUT REGISTER AND DAC LATCH
The DAC9881 is controlled by a versatile three-wire serial interface that operates at clock rates of up to 50MHz
and is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards.
Data are loaded into the device as a 24-bit word under the control of the serial clock input, SCLK. The timing
diagrams for this operation are shown in the Timing Diagram section.
The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be
transferred into the device only while CS is low. When CS is high, the SCLK and SDI signals are blocked out,
and SDO is in high-Z status. To start the serial data transfer, CS should be taken low, observing the minimum
delay from CS falling edge to SCLK rising edge, t2. After CS goes low, serial input data from SDI are clocked into
the device input shift register on the rising edges of SCLK for 24 or more clock pulses. If a frame contains less
than 24 bits of data, the frame is invalid. Invalid input data are not written into the input register and DAC,
although the input register and DAC will continue to hold data from the preceding valid data cycle. If more than
24 bits of data are transmitted in one frame, the last 24 bits are written into the shift register and DAC. CS may
be taken high after the rising edge of the 24th SCLK pulse, observing the minimum SCLK rising edge to CS
rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of
CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and
DAC output can be updated by taking the LDAC pin low. Table 4 shows the input shift register data word format.
D17 is the MSB of the 18-bit DAC data.
Table 4. Input Shift Register Data Word Format
X = don't care.
When the SDOSEL pin is tied to IOVDD, the interface is in Stand-Alone mode. This mode provides serial
readback for diagnostic purposes. The new input data (24 bits) are clocked into the device shift register and the
existing data in the input register (24 bits) are shifted out from the SDO pin. If more than 24 SCLKs are clocked
when CS is low, the contents of the input register are shifted out from the SDO pin, followed by zeroes; the last
24 bits of input data remain in the shift register. If less than 24 SCLKs are clocked while CS is low, the data from
the SDO pin are part of the data in the input register and must be ignored. Refer to Figure 2 for further details.
When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several
DACs, the SDO pin may be used to daisy-chain several devices together.