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DAC9881B Datasheet(数据表) 7 Page - Texas Instruments

部件型号  DAC9881B
说明  18-Bit, Single-Channel, Low-Noise, Voltage-Output DIGITAL-TO-ANALOG CONVERTER
下载  39 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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 7 page
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PIN CONFIGURATION
SCLK
SDI
LDAC
AGND
AV
DD
V
-S
REFL
(ThermalPad)
(1)
PDN
RST
USB/BTC
GAIN
RSTSEL
NC
1
2
3
4
5
6
18
17
16
15
14
13
DAC9881
DAC9881
www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008
RGE PACKAGE(1)
QFN-24
(TOP VIEW)
(1)
The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left
floating. Keep the thermal pad separate from the digital ground, if possible.
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
I/O
DESCRIPTION
1
SCLK
I
SPI bus serial clock input
2
SDI
I
SPI bus serial data input
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input
3
LDAC
I
register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the
DAC latch is updated. It is recommended to connect this pin to IOVDD through a pull-up resistor.
4
AGND
I
Analog ground
5
AVDD
I
Analog power supply
6
VREFL-S
I
Reference low input sense
7
VREFH-S
I
Reference high input sense
8
VOUT
O
Output of output buffer
9
RFB
I
Feedback resistor connected to the inverting input of the output buffer.
10
VREFL-F
I
Reference low input force
11
VREFH-F
I
Reference high input force
12
NC
Do not connect.
13
NC
Do not connect.
Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data
14
RSTSEL
I
= 20000h. If RSTSEL = DGND, then register data = 00000h.
15
GAIN
I
Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD.
Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in twos
16
USB/BTC
I
complement format when the pin is connected to DGND.
17
RST
I
Reset input (active low). Logic low on this pin causes the device to perform a reset.
Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT
18
PDN
I
pin connects to AGND through a 10k
Ω resistor.
SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is
19
CS
I
high, SDO is in a high-impedance state. It is recommended to connect this pin to IOVDD through a pull-up resistor.
SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out
20
SDOSEL
I
from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register
are shifted out from the SDO pin; this is Daisy-Chain mode for daisy-chained communication.
21
AVDD
I
Analog power supply. Must be connected to pin 5.
22
DGND
I
Digital ground
23
SDO
O
SPI bus serial data output. Refer to the Timing Diagrams for further detail.
24
IOVDD
I
Interface power. Connect to +1.8V for 1.8V logic, +3V for 3V logic, and to +5V for 5V logic.
Copyright © 2008, Texas Instruments Incorporated
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