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DAC7614E 数据表(PDF) 11 Page - Texas Instruments |
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DAC7614E 数据表(HTML) 11 Page - Texas Instruments |
11 / 17 page 11 ® DAC7614 STATE OF SELECTED SELECTED DAC DAC A1 A0 LOADDACS RESET REGISTER REGISTER L(1) L L H A Transparent L H L H B Transparent H L L H C Transparent H H L H D Transparent X(2) X H H NONE (All Latched) X X X L ALL Reset(3) NOTES: (1) L = Logic LOW. (2) X = Don’t Care. (3) Resets to either 000H or 800H, per the RESETSEL state (LOW = 000H, HIGH = 800H). When RESET rises, all registers that are in their latched state retain the reset value. TABLE II. Control Logic Truth Table. CS(1) CLK(1) LOADDACS RESET SERIAL SHIFT REGISTER H(2) X(3) H H No Change L(4) L H H No Change L ↑(5) H H Advanced One Bit ↑ L H H Advanced One Bit H(6) XL(7) H No Change H(6) XH L(8) No Change NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOADDACS is LOW, the selected DAC register will change as the shift register bits “flow” through A1 and A0. This will corrupt the data in each DAC register that has been erroneously selected. (8) RESET LOW causes no change in the contents of the serial shift register. TABLE III. Serial Shift Register Truth Table. Note that CS and CLK are combined with an OR gate and the output controls the serial-to-parallel shift register inter- nal to the DAC7614 (see the block diagram on the front of this data sheet). These two inputs are completely inter- changeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong DAC. If both CS and CLK are used, then CS should rise only when CLK is HIGH. If not, then either CS or CLK can be used to operate the shift register. See Table III for more information. Digital Input Coding The DAC7614 input data is in Straight Binary format. The output voltage is given by the following equation: where N is the digital input code (in decimal). This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. (VREFH – VREFL) • N 4096 VOUT = VREFL + |
类似零件编号 - DAC7614E |
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类似说明 - DAC7614E |
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