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DAC37J84IAAV Datasheet(数据表) 86 Page - Texas Instruments

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部件型号  DAC37J84IAAV
说明  Digital-to-Analog Converters
下载  122 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DAC37J84IAAV Datasheet(HTML) 86 Page - Texas Instruments

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DAC37J84, DAC38J84
SLASE17B – JANUARY 2014 – REVISED MARCH 2014
www.ti.com
Register Name: config74 – Address: 0x4A, Default: 0x001E
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config74
0x4A
15:8
lane_ena
Turn on each SerDes lane as needed. Signal is active high.
0x00
bit15 : SerDes lane7 enable
bit14 : SerDes lane6 enable
bit13 : SerDes lane5 enable
bit12 : SerDes lane4 enable
bit11 : SerDes lane3 enable
bit10 : SerDes lane2 enable
bit9 : SerDes lane1 enable
bit8 : SerDes lane0 enable
7:6
jesd_test_seq Set to select and verify link layer test sequences. The error for these
00
sequences comes out the lane alarms bit0. 1= fail and 0 = pass.
00 : test sequence disabled
01 : verify repeating D.21.5 high frequency pattern for random jitter
10 : verify repeating K.28.5 mixed frequency pattern for deterministic jitter
11 : verify repeating ILA sequence
5
dual
Turn on “DUAL DAC” mode. This disables the clocks to the C and D data
0
paths, reducing the power of the DIG block.
4:1
init_ state
Put the JESD block into “INIT_STATE” mode when high. During this mode the
1111
JESD can be programmed and its outputs will stay at zero. NOTE: See the
JESD description of the correct startup sequence.
0
jesd_ reset_n Reset the JESD block when low. NOTE: See the JESD description of the
0
correct startup sequence.
Register Name: config75 – Address: 0x4B, Default: 0x0000
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config75
0x4B
15:13
reserved
Reserved
000
12:8
rbd_m1
This controls the amount of elastic buffers being used in the JESD. Larger
00000
numbers will mean more latency, but smaller numbers may not hold enough
data to capture the input skew. This value must always be
≤ k_m1
7:0
f_m1
This is the number of octets in the frame. The DAC37J84/DAC38J84 only
0x00
supports 1,2,4 or 8 octets per frame so the only valid values are 0,1,3, and 7.
Register Name: config76 – Address: 0x4C, Default: 0x0000
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config76
0x4C
15:13
reserved
Reserved
000
12:8
k_m1
This is the number of frames in a multi-frame. The range is 0-31.
00000
7
reserved
Reserved
0
6
reserved
Reserved
0
5
reserved
Reserved
0
4:0
l_m1
This is the number of lanes used by the JESD. Possible values are 0-7.
00000
Register Name: config77 – Address: 0x4D, Default: 0x0300
Register
Addr
Default
Bit
Name
Function
Name
(Hex)
Value
config77
0x4D
15:8
m_m1
This is the number of converters per link. NOTE: Valid programmed values
0x03
are 0, 1 and 3.
7:5
reserved
Reserved
000
4:0
s_m1
This is the number of converter samples per frame. NOTE: Valid
00000
programming is 0 or 1.
86
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Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DAC37J84 DAC38J84




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