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DAC37J84IAAV Datasheet(数据表) 49 Page - Texas Instruments

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部件型号  DAC37J84IAAV
说明  Digital-to-Analog Converters
下载  122 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DAC37J84IAAV Datasheet(HTML) 49 Page - Texas Instruments

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DAC37J84, DAC38J84
www.ti.com
SLASE17B – JANUARY 2014 – REVISED MARCH 2014
Table 20. IEEE1500 Instruction for SerDes Receivers
INSTRUCTION
OPCODE
DESCRIPTION
ws_bypass
0x00
Bypass. Selects a 1-bit bypass data register. Use when accessing other macros on the same IEEE1500
scan chain.
ws_cfg
0x35
Configuration. Write protection options for other instructions.
ws_core
0x30
Core. Fields also accessible via dedicated core-side ports.
ws_tuning
0x31
Tuning. Fields for fine tuning macro performance.
ws_debug
0x32
Debug. Fields for advanced control, manufacturing test, silicon characterization and debug
ws_unshadowed
0x34
Unshadowed. Fields for silicon characterization.
ws_char
0x33
Char. Fields used for eye scan.
The data for each SerDes instruction is formed by chaining together sub-components called head, body (receiver
or transmitter) and tail. DAC37J84/DAC38J84 uses two SerDes receiver blocks R0 and R1, each of which
contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head,
receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail
for each instruction is given as follows:
NOTE
All multi-bit signals in each chain are packed with bits reversed e.g. mpy[7:0] in ws_core
head subchain is packed as {retime, enpll, mpy[0:7], vrange,lb[0:1]}. All DATA REGISTER
READS from SerDes Block R0 should read 1 bit more than the desired number of bits and
discard the first bit received on TDO e.g., to read 40-bit data from R0 block, 41 bits should
be read off from TDO and the first bit received should be discarded. Similarly, any data
written to SerDes Block R0 Data Registers should be prefixed with an extra 0.
Table 21. ws_cfg Chain
FIELD
DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME
No function.
CORE_WE
Core chain write enable.
RECEIVER (FOR EACH LANE 0,1,2,3)
CORE_WE
Core chain write enable.
TUNING_WE
Tuning chain write enable.
DEBUG_WE
Reserved.
CHAR_WE
Char chain write enable.
UNSHADOWED_WE
Reserved.
TAIL (ENDING WITH THE LSB OF CHAIN)
CORE_WE
Core chain write enable.
TUNING_WE
Tuning chain write enable.
DEBUG_WE
Reserved.
RETIME
No function.
CHAIN LENGTH = 26 BITS
Table 22. ws_core Chain
FIELD
DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME
No function.
ENPLL
PLL enable.
MPY[7:0]
PLL multiply.
VRANGE
VCO range.
ENDIVCLK
Enable DIVCLK output
Copyright © 2014, Texas Instruments Incorporated
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49
Product Folder Links: DAC37J84 DAC38J84




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