54ACT11000, 74ACT11000

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCAS002A – D2957, JUNE 1987 – REVISED APRIL 1993

POST OFFICE BOX 655303

Copyright

2–1

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

mm Process

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and

Ceramic 300-mil DIPs

description

These devices contain four independent 2-input

NAND gates. They perform the Boolean functions

Y = A

SB or Y = A + B in positive logic.

The 54ACT11000 is characterized for operation

over the full military temperature range of – 55

°C

to 125

°C. The 74ACT11000 is characterized for

operation from – 40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

H

H

L

L

XH

X

L

H

7

6

3

2

4B

4A

3B

3A

2B

2A

1B

1A

4Y

3Y

2Y

1Y

8

9

10

11

14

15

16

1

&

logic diagram (positive logic)

1Y

1A

1B

2Y

2A

2B

3Y

3A

3B

4Y

4A

4B

† This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

54ACT11000 ...J PACKAGE

74ACT11000 ...D OR N PACKAGE

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1A

1Y

2Y

GND

GND

3Y

4Y

4B

1B

2A

2B

3A

3B

4A

(TOP VIEW)

3

2

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

3B

4A

NC

4B

4Y

2A

1B

NC

1A

1Y

54ACT11000 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.