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AM1802EZCED3 数据表(PDF) 1 Page - Texas Instruments

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部件名 AM1802EZCED3
功能描述  AM1802 ARM짰 Microprocessor
Download  182 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

AM1802EZCED3 数据表(HTML) 1 Page - Texas Instruments

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AM1802
SPRS710E – NOVEMBER 2010 – REVISED MARCH 2014
AM1802 ARM® Microprocessor
1
AM1802 ARM Microprocessor
1.1
Features
1
• 300-MHz ARM926EJ-S™ RISC MPU
• Two Serial Peripheral Interfaces (SPIs) Each with
Multiple Chip Selects
• ARM926EJ-S Core
• One Multimedia Card (MMC)/Secure Digital (SD)
– 32-Bit and 16-Bit ( Thumb®) Instructions
Card Interfaces with Secure Data I/O (SDIO)
– Single-Cycle MAC
Interfaces
– ARM Jazelle® Technology
• One Master and Slave Inter-Integrated Circuit ( I2C
– Embedded ICE-RT™ for Real-Time Debug
Bus™)
• ARM9™ Memory Architecture
• USB 2.0 OTG Port with Integrated PHY (USB0)
– 16KB of Instruction Cache
– USB 2.0 High- and Full-Speed Client
– 16KB of Data Cache
– USB 2.0 High-, Full-, and Low-Speed Host
– 8KB of RAM (Vector Table)
– End Point 0 (Control)
– 64KB of ROM
– End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or
• Enhanced Direct Memory Access Controller 3
ISOC) RX and TX
(EDMA3):
• One Multichannel Audio Serial Port (McASP):
– 2 Channel Controllers
– Transmit and Receive Clocks
– 3 Transfer Controllers
– Two Clock Zones and 16 Serial Data Pins
– 64 Independent DMA Channels
– Supports TDM, I2S, and Similar Formats
– 16 Quick DMA Channels
– DIT-Capable
– Programmable Transfer Burst Size
– FIFO Buffers for Transmit and Receive
• 128KB of On-Chip Memory
• 10/100 Mbps Ethernet MAC (EMAC):
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
– IEEE 802.3 Compliant
DDR2 Interfaces)
– MII Media-Independent Interface
• Two External Memory Interfaces:
– RMII Reduced Media-Independent Interface
– EMIFA
– Management Data I/O (MDIO) Module
NOR (8- or 16-Bit-Wide Data)
• Real-Time Clock (RTC) with 32-kHz Oscillator and
NAND (8- or 16-Bit-Wide Data)
Separate Power Rail
16-Bit SDRAM with 128-MB Address Space
• Three 64-Bit General-Purpose Timers (Each
– DDR2/Mobile DDR Memory Controller with one
Configurable as Two 32-Bit Timers)
of the following:
• One 64-Bit General-Purpose or Watchdog Timer
16-Bit DDR2 SDRAM with 256-MB Address
(Configurable as Two 32-Bit General-Purpose
Space
Timers)
16-Bit mDDR SDRAM with 256-MB Address
• Packages:
Space
– 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
• Three Configurable 16550-Type UART Modules:
[ZCE Suffix], 0.65-mm Ball Pitch
– With Modem Control Signals
– 361-Ball PBGA [ZWT Suffix], 0.80-mm Ball Pitch
– 16-Byte FIFO
• Industrial Temperature
– 16x or 13x Oversampling Option
1.2
Applications
Medical, Healthcare, and Fitness
ePOS
Building Automation
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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