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ADC108S102CIMT 数据表(PDF) 6 Page - Texas Instruments |
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ADC108S102CIMT 数据表(HTML) 6 Page - Texas Instruments |
6 / 27 page ADC108S102 SNAS336B – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ADC108S102 Timing Specifications The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1 MSPS, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Limits Symbol Parameter Conditions Typical Units (1) tCSH CS Hold Time after SCLK Rising Edge 0 10 ns (min) CS Setup Time prior to SCLK Rising tCSS 5 10 ns (min) Edge tEN CS Falling Edge to DOUT enabled 5 30 ns (max) DOUT Access Time after SCLK Falling tDACC 17 27 ns (max) Edge DOUT Hold Time after SCLK Falling tDHLD 4 ns (typ) Edge DIN Setup Time prior to SCLK Rising tDS 3 10 ns (min) Edge tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min) tCH SCLK High Time 0.4 x tSCLK ns (min) tCL SCLK Low Time 0.4 x tSCLK ns (min) DOUT falling 2.4 20 ns (max) CS Rising Edge to DOUT High- tDIS Impedance DOUT rising 0.9 20 ns (max) (1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level). 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC108S102 |
类似零件编号 - ADC108S102CIMT |
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类似说明 - ADC108S102CIMT |
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