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ADC108S022 数据表(PDF) 6 Page - Texas Instruments |
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ADC108S022 数据表(HTML) 6 Page - Texas Instruments |
6 / 25 page tCSH SCLK CS tCSS CS tCONVERT tACQ tCH tCL tEN tDH tDS FOUR ZEROS DB8 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC DB9 DB7 DB6 B1 14 8 7 6 5 4 3 2 1 DB0 DIN DOUT SCLK CS tDIS 15 16 tDACC tDHLD TWO ZEROS 8 9 10 11 12 13 14 15 16 Track Hold Power Up ADD2 ADD1 ADD0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DIN DOUT SCLK CS Control register 1 2 3 4 5 6 7 1 2 3 4 5 6 7 ADD2 ADD1 ADD0 8 DB9 DB8 DB7 Power Down Power Up Track Hold FOUR ZEROS SIX ZEROS ADC108S022 SNAS338F – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ADC108S022 Timing Specifications (continued) The following specifications apply for VA = VD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Limits Symbol Parameter Conditions Typical Units (1) DOUT falling 2.4 20 ns (max) CS Rising Edge to DOUT High- tDIS Impedance DOUT rising 0.9 20 ns (max) Timing Diagrams Figure 2. ADC108S022 Operational Timing Diagram Figure 3. ADC108S022 Serial Timing Diagram Figure 4. SCLK and CS Timing Parameters 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC108S022 |
类似零件编号 - ADC108S022_15 |
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类似说明 - ADC108S022_15 |
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