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ADCS7476, ADCS7477, ADCS7478

SNAS192G – APRIL 2003 – REVISED MAY 2016

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Timing Requirements (continued)

–40°C

(1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

(4)

Measured with the load circuit (Figure 1), and defined as the time taken by the output to cross 1 V or 2 V.

(5)

of the bus loading.

40

ns

20

ns

SCLK low pulse width

ns

SCLK high pulse width

ns

SCLK to data valid hold time

7

ns

5

ns

SCLK falling edge to SDATA high

6

25

ns

5

25

ns

Power-up time from full power down

1

µs

Figure 1. Timing Test Circuit

Figure 2. ADCS7476 Serial Interface Timing Diagram