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DM54LS181J 数据表(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 DM54LS181J
功能描述  4-Bit Arithmetic Logic Unit
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

DM54LS181J 数据表(HTML) 5 Page - National Semiconductor (TI)

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Logic Mode Test Table III
Function Inputs S1 e S2 e M e 45V S0 e S3 e 0V
Input
Other Input
Other Data Inputs
Output
Symbol
Under
Same Bit
Under
Test
Apply
Apply
Apply
Apply
Test
45V
GND
45V
GND
tPLH
A
B
None
None
Remaining
Any F
tPHL
A and B Cn
tPLH
B
A
None
None
Remaining
Any F
tPHL
A and B Cn
Functional Description
The ’LS181 is a 4-bit high speed parallel Arithmetic Logic
Unit (ALU) Controlled by the four Function Select inputs
(S0 – S3) and the Mode Control input (M) it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands The
Function Table lists these operations
When the Mode Control input (M) is HIGH all internal car-
ries are inhibited and the device performs logic operations
on the individual bits as listed When the Mode Control input
is LOW the carries are enabled and the device performs
arithmetic operations on the two 4-bit words The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cna4 output
or for carry lookahead between packages using the signals
P (Carry Propagate) and G (Carry Generate) In the ADD
mode P indicates that F is 15 or more while G indicates
that F is 16 or more In the SUBTRACT mode P indicates
that F is zero or less while G indicates that F is less than
zero P and G are not affected by carry in When speed
requirements are not stringent it can be used in a simple
ripple carry mode by connecting the Carry output (Cna4)
signal to the Carry input (Cn) of the next unit For high speed
operation the device is used in conjunction with the 9342 or
93S42 carry lookahead circuit One carry lookahead pack-
age is required for each group of four ’LS181 devices Carry
lookahead can be provided at various levels and offers high
speed capability over extremely long word lengths
The A e B output from the device goes HIGH when all four
F outputs are HIGH and can be used to indicate logic equiv-
alence over four bits when the unit is in the subtract mode
The A e B output is open-collector and can be wired-AND
with other A e B outputs to give a comparison for more
than four bits The A e B signal can also be used with the
Cna4 signal to indicate A l B and A k B
The Function Table lists the arithmetic operations that are
performed without a carry in An incoming carry adds a one
to each operation Thus select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied Be-
cause subtraction is actually performed by complementary
addition (1s complement) a carry out means borrow thus a
carry is generated when there is no underflow and no carry
is generated when there is underflow As indicated this de-
vice can be used with either active LOW inputs producing
active LOW outputs or with active HIGH inputs producing
active HIGH outputs For either case the table lists the oper-
ations that are performed to the operands labeled inside the
logic symbol
Function Table
Mode Select
Active LOW Operands
Active HIGH Operands
Inputs
Fn Outputs
Fn Outputs
Logic
Arithmetic
Logic
Arithmetic
S3
S2
S1
S0
(M e H)
(M e L) (Cn e L)
(M e H)
(M e L) (Cn e H)
LLLL
A
A minus 1
A
A
LLL
H
AB
AB minus 1
A a B
A a B
L
LHL
A a B
AB minus 1
ABA a B
L
L
H
H
Logic 1
minus 1
Logic 0
minus 1
LHL
L
A a B
A plus (A a B)AB
A plus AB
LHLH
B
AB plus (A a B)B
(A a B) plus AB
LH
HL
A Z B
A minus B minus 1
A Z B
A minus B minus 1
L
HHH
A a B
A a B
AB
AB minus 1
H
LLL
AB
A plus (A a B)
A a B
A plus AB
HL
LH
A Z B
A plus B
A Z B
A plus B
HLHL
B
AB plus (A a B)
B
(A a B) plus AB
HLH
H
A a BA a B
AB
AB minus 1
H
H
L
L
Logic 0
A plus A
Logic 1
A plus A
H
HLH
AB
AB plus A
A a B
(A a B) plus A
HHH
L
AB
AB minus A
A a B(A a B) plus A
HHHH
A
A
A
A minus 1
Each bit is shifted to the next most significant position
Arithmetic operations expressed in 2s complement notation
5


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