10

LT1970

1970f

APPLICATIO S I FOR ATIO

active and because of its very high transconductance,

takes control from the input stage, GM1. The output

gether, with the load on the opposite side of the external

allow other connections. Ground side sensing of load

current may be employed by connecting the load between

ground in this instance. Load current would be regulated

in exactly the same way as the conventional connection.

However, voltage mode accuracy would be degraded in

operating principle that at most one of the current limit

stages may be active at one time, and that when active, the

current limit stages take control of the output from GM1,

can be used for many different signals.

Current Limit Threshold Control Buffers

Each of these inputs may be independently driven by a

voltage of 0V to 5V above the COMMON reference pin. The

0V to 5V input voltage is attenuated by a factor of 10 and

applied as an offset to the appropriate current limit ampli-

fier. AC signals may be applied to these pins. The AC

linear from about 0.1V to 5V in, or 10mV to 500mV at the

current limit amplifier inputs. An intentional nonlinearity is

built into the transfer functions at low levels. This nonlin-

earity insures that both the sink and source limit amplifiers

cannot become active simultaneously. Simultaneous acti-

vation of the limit amplifiers could result in uncontrolled

outputs. As shown in the Typical Performance Character-

istics curves, the control inputs have a “hockey stick”

shape, to keep the minimum limit threshold at 4mV for

each limit amplifier.

ENABLE Control

The ENABLE input pin puts the LT1970 into a low supply

current, high impedance output state. The ENABLE pin

responds to TTL threshold levels with respect to the

COMMON pin. Pulling the ENABLE pin low is the best way

= 0V allows the output current to remain as high as

Operating Status Flags

The LT1970 has three digital output indicators; TSD, ISRC

and ISNK. These outputs are open collector drivers re-

ferred to the COMMON pin. The outputs have 36V capabili-

ties and can sink in excess of 10mA. ISRC and ISNK

indicate activation of the associated current limit ampli-

fier. The TSD output indicates excessive die temperature

has caused the circuit to enter thermal shutdown. The

three digital outputs may be wire “OR’d” together, moni-

tored individually or left open. These outputs do not affect

circuit operation, but provide an indication of the present

operational status of the chip.

THERMAL MANAGEMENT

Minimizing Power Dissipation

The LT1970 can operate with up to 36V total supply

voltage with output currents up to

±500mA. The amount

of power dissipated in the chip could approach 18W under

worst-case conditions. This amount of power will cause

die temperature to rise until the circuit enters thermal

shutdown. While the thermal shutdown feature prevents

damage to the circuit, normal operation is impaired.

Thermal design of the LT1970 operating environment is

essential to getting maximum utility from the circuit.

The first concern for thermal management is minimizing

the heat which must be dissipated. The separate power

even under maximum output current conditions. Using

separate power supplies, or off chip dissipative elements,

output swing will minimize power dissipation. The sup-