DM54L74J datasheet(3/4 Pages) NSC

部件名	DM54L74J

功能描述	Dual Positive-Edge-Triggered D Flip-Flops

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制造商	NSC [National Semiconductor (TI)]

网页	http://www.national.com

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3 / 4 page

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(Note 1)

VOH

High Level Output

VCC e Min IOH e Max

24

33

V

Voltage

VIL e Max VIH e Min

VOL

Low Level Output

VCC e Min IOL e Max

015

03

V

Voltage

VIL e Max VIH e Min

II

Input Current

Max

VCC e Max

D

100

Input Voltage

VI e 55V

Clear

300

m

A

Preset

200

Clock

200

IIH

High Level Input

VCC e Max

D

10

Current

VI e 24V

Clear

30

m

A

Preset

20

Clock

20

IIL

Low Level Input

VCC e Max

D

b

018

Current

VI e 03V

Clear

b

036

mA

Preset

b

018

Clock

b

036

IOS

Short Circuit

VCC e Max

b

3

b

15

mA

Output Current

ICC

Supply Current

VCC e Max (Note 2)

16

3

mA

Note 1

All typicals are at VCC e 5V TA e 25 C

Note 2

With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock input is grounded

Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)

Symbol

Parameter

From (Input)

RL e 4kX CL e 50 pF

Units

To (Output)

Min

Max

fMAX

Maximum Clock Frequency

6

MHz

tPLH

Propagation Delay Time

Preset

60

ns

Low to High Level Output

to Q

tPHL

Propagation Delay Time

Preset

120

ns

High to Low Level Output

to Q

tPLH

Propagation Delay Time

Clear

60

ns

Low to High Level Output

to Q

tPHL

Propagation Delay Time

Clear

120

ns

High to Low Level Output

to Q

tPLH

Propagation Delay Time

Clock to

10

90

ns

Low to High Level Output

Q or Q

tPHL

Propagation Delay Time

Clock to

10

120

ns

High to Low Level Output

Q or Q

3

类似零件编号 - DM54L74J

制造商	部件名	数据表	功能描述
National Semiconductor ...	DM54L72	89Kb / 4P	AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs
	DM54L72J	89Kb / 4P	AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs
	DM54L72W	89Kb / 4P	AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear and Complementary Outputs
	DM54L73	88Kb / 4P	Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
	DM54L73J	88Kb / 4P	Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

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类似说明 - DM54L74J

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Texas Instruments	SN54LV74	148Kb / 8P	[Old version datasheet] DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
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