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74HCT2G125DP 数据表(PDF) 2 Page - NXP Semiconductors |
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74HCT2G125DP 数据表(HTML) 2 Page - NXP Semiconductors |
2 / 20 page 2003 Mar 03 2 Philips Semiconductors Product specification Dual buffer/line driver; 3-state 74HC2G125; 74HCT2G125 FEATURES • Wide supply voltage range from 2.0 to 6.0 V • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • Very small 8 pins package • Output capability: bus driver • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74HC2G/HCT2G125 is a high-speed Si-gate CMOS device. The 74HC2G/HCT2G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input pin (OE). A HIGH at pin OE causes the output to assume a high-impedance OFF-state. The bus driver output currents are equal compared to the 74HC/HCT125. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 6.0 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC2G125 the condition is VI = GND to VCC. For 74HCT2G125 the condition is VI = GND to VCC − 1.5 V. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC2G HCT2G tPHL/tPLH propagation delay nA to nY CL = 15 pF; VCC = 5 V 1012ns CI input capacitance 1.0 1.0 pF CO output capacitance 1.5 1.5 pF CPD power dissipation capacitance per buffer output enabled; notes 1 and 2 11 11 pF output disabled; notes 1 and 2 1 1 pF |
类似零件编号 - 74HCT2G125DP |
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类似说明 - 74HCT2G125DP |
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