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CSC08A03KGEK 数据表(PDF) 5 Page - Vishay Siliconix

部件名 CSC08A03KGEK
功能描述  Thick Film Resistor Networks, Single-In-Line, Conformal Coated SIP
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制造商  VISHAY [Vishay Siliconix]
网页  http://www.vishay.com
标志 VISHAY - Vishay Siliconix

CSC08A03KGEK 数据表(HTML) 5 Page - Vishay Siliconix

  CSC08A03KGEK Datasheet HTML 1Page - Vishay Siliconix CSC08A03KGEK Datasheet HTML 2Page - Vishay Siliconix CSC08A03KGEK Datasheet HTML 3Page - Vishay Siliconix CSC08A03KGEK Datasheet HTML 4Page - Vishay Siliconix CSC08A03KGEK Datasheet HTML 5Page - Vishay Siliconix CSC08A03KGEK Datasheet HTML 6Page - Vishay Siliconix  
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CSC
www.vishay.com
Vishay Dale
Revision: 03-May-13
5
Document Number: 31509
For technical questions, contact: ff2aresistors@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
CIRCUIT APPLICATIONS
01 Schematic
Bussed
The CSCxxx01 single-in-line resistor networks provide the user with
nominally equal resistors, each connected to a common pin (pin no. 1).
Commonly used in the following applications:
• “Wired OR” pull-up
• Open collector pull-up
• Power gate pull-up
• TTL input pull-down
• MOS/ROM pull-up/pull-down
• TTL unused gate pull-up
* “A” profile standard, “B” profile available.
03 Schematic
Isolated
The CSCxxx03 single-in-line resistor networks provide the user with
nominally equal resistors. Each resistor is isolated from all others.
Commonly used in the following applications:
• “Wired OR” pull-up
• Long-line impedance balancing
• Power driven pull-up
• LED current limiting
• Power gate pull-up
• ECL output pull-down
• Line termination
• TTL input pull-down
* “A” Profile standard, “B” profile available.
05 Schematic
Dual Terminator
The CSCxxx05 circuits contain series pairs of resistors. Each series
pair is connected between two common lines. The junction of these
resistor pairs is connected to the input terminals. The 05 circuits are
designed for TTL dual-line termination and pulse squaring.
* “A” profile standard, “B” profile available.
PERFORMANCE
TEST
CONDITIONS
MAX.
R (TYPICAL TEST LOTS)
Thermal shock
5 cycles between - 65 °C and + 125 °C
± 0.50 %
R
Short time overload
2.5 x rated working voltage, 5 s
± 0.25 %
R
Low temperature operation
45 min at full rated working voltage at - 65 °C
± 0.25 %
R
Moisture resistance
240 h with humidity ranging from 80 % RH to 98 % RH
± 1.00 %
R
Resistance to soldering heat
Leads immersed in + 350 °C solder to within 1/16" of body for 3 s
± 0.25 %
R
Shock
Total of 18 shocks at 100 g's
± 0.25 %
R
Vibration
12 h at maximum of 20 g's between 10 Hz and 2000 Hz
± 0.25 %
R
Load life
1000 h at + 70 °C, rated power applied 1.5 h “ON”, 0.5 h “OFF” for full
1000 h period. Derated according to the curve.
± 1.00 %
R
Terminal strength
4.5 pound pull for 30 s
± 0.25 %
R
Insulation resistance
10 000 M
 (minimum)
-
Dielectric withstanding voltage
No evidence of arcing or damage (200 VRMS for 1 min)
-
1
2
3
n-1
n
1
2
3
4
n-1
n
1
2
3
n-1
n
R1
R2


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