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GM76C256CLLET 数据表(PDF) 8 Page - Hynix Semiconductor

部件名 GM76C256CLLET
功能描述  32K x8 bit 5.0V Low Power CMOS slow SRAM
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

GM76C256CLLET 数据表(HTML) 8 Page - Hynix Semiconductor

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GM76C256C Series
Rev 03 / Apr. 2000
7
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high
and /WE going high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS,
or /WE going high.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high
impedance state.
7. DOUT is the same phase of the latest written data in this write cycle.
8. DOUT is the read data of the new address.
DATA RETENTION CHARACTERISTIC
TA = 0
°C to 70°C (Normal) / -25°C to 85°C (Extended) unless otherwise specified.
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VDR
Vcc for Data Retention
CS>Vcc-0.2V,
2.0
-
-
V
VIN > Vcc - 0.2V or VIN < Vss + 0.2V
ICCDR
Data Retention Current
Vcc=3.0V,
L
-
1
15
uA
/CS>Vcc - 0.2V,
LL
-
0.5
7
uA
VIN > Vcc - 0.2V or
LE
-
1
20
uA
VIN < Vss + 0.2V
LLE
-
0.5
10
uA
tCDR
Chip Deselect to Data
Retention Time
See Data Retention
0
-
-
ns
tR
Operating Recovery Time
Timing Diagram
tRC(2)
-
-
ns
Notes
1. Typical values are under the condition of TA = 25
°C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
CS
VDR
CS>VCC-0.2V
tCDR
tR
VSS
VCC
4.5V
2.2V
DATA RETENTION MODE


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