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ADUM210N1BRIZ 数据表(PDF) 6 Page - Analog Devices |
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ADUM210N1BRIZ 数据表(HTML) 6 Page - Analog Devices |
6 / 15 page ADuM210N Data Sheet Rev. 0 | Page 6 of 15 Table 6. Total Supply Current vs. Data Throughput—2.5 V Operation 1 Mbps 25 Mbps 100 Mbps Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit SUPPLY CURRENT Supply Current Side 1 IDD1 2.2 3.4 2.4 3.6 3.2 4.3 mA Supply Current Side 2 IDD2 0.9 1.4 1.3 1.8 2.3 3.5 mA ELECTRICAL CHARACTERISTICS—1.8 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals. Table 7. Parameter Symbol Min Typ Max Unit Test Conditions/Comments SWITCHING SPECIFICATIONS Pulse Width PW 6.6 ns Within PWD limit Data Rate 150 Mbps Within PWD limit Propagation Delay tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output Pulse Width Distortion PWD 0.7 3 ns |tPLH − tPHL| Change vs. Temperature 1.5 ps/°C Propagation Delay Skew tPSK 7.0 ns Between any two units at the same temperature, voltage, and load Jitter 630 ps p-p See the Jitter Measurement section 190 ps rms See the Jitter Measurement section DC SPECIFICATIONS Input Threshold Logic High VIH 0.7 × VDD1 V Logic Low VIL 0.3 × VDD1 V Output Voltage Logic High VOH VDD2 − 0.1 VDD2 V IO = −20 µA, VI = VIH VDD2 − 0.4 VDD2 − 0.2 V IO = −2 mA, VI = VIH Logic Low VOL 0.0 0.1 V IO = 20 µA, VI = VIL 0.2 0.4 V IO = 2 mA, VI = VIL Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VI ≤ VDD1 Quiescent Supply Current IDD1 (Q) 0.7 1.1 mA VI = 0 (N0), 1 (N1)1 IDD2 (Q) 0.9 1.2 mA VI = 0 (N0), 1 (N1)1 IDD1 (Q) 3.4 5.4 mA VI = 1 (N0), 0 (N1)1 IDD2 (Q) 0.9 1.2 mA VI = 1 (N0), 0 (N1)1 Dynamic Supply Current Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle Undervoltage Lockout UVLO Positive VDDx Threshold VDDxUV+ 1.6 V Negative VDDx Threshold VDDxUV− 1.5 V VDDx Hysteresis VDDxUVH 0.1 V AC SPECIFICATIONS Output Rise/Fall Time tR/tF 2.5 ns 10% to 90% Common-Mode Transient Immunity2 |CMH| 75 100 kV/µs VI = VDD1, VCM = 1000 V, transient magnitude = 800 V |CML| 75 100 kV/µs V1 = 0 V, VCM = 1000 V, transient magnitude = 800 V 1 N0 indicates the ADuM210N0 models and N1 indicates the ADuM210N1 models. See the Ordering Guide. 2 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 × VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. |
类似零件编号 - ADUM210N1BRIZ |
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