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AD7172-4 数据表(PDF) 9 Page - Analog Devices |
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AD7172-4 数据表(HTML) 9 Page - Analog Devices |
9 / 61 page Data Sheet AD7172-4 Rev. A | Page 9 of 61 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 AIN3 23 AIN2 22 GPO2 21 GPIO1 20 GPIO0 19 REGCAPD 18 DGND 17 IOVDD 1 2 3 4 5 6 7 8 AIN0/REF2– AIN1/REF2+ DNC REGCAPA AVSS AVDD1 AVDD2 PDSW AD7172-4 TOP VIEW (Not to Scale) NOTES 1. DNC = DO NOT CONNECT. 2. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH TO THE PACKAGE AND FOR HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB. Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 AIN0/REF2− AI Analog Input 0/Reference 2 Negative Input Terminal. A reference can be applied between the REF2+ and REF2− pins. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through the crosspoint multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration (SETUPCONx) registers. 2 AIN1/REF2+ AI Analog Input 1/Reference 2 Positive Input Terminal. A reference can be applied between the REF2+ and REF2− pins. REF2+ can span from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through the crosspoint multiplexer. Reference 2 can be selected through the REF_SELx bits in the setup configuration (SETUPCONx) registers. 3 DNC Do Not Connect. Do not connect to this pin. 4 REGCAPA AO Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor. 5 AVSS P Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V. 6 AVDD1 P Analog Supply Voltage 1. This voltage ranges from 3.0 V minimum to 5.5 V maximum with respect to AVSS. 7 AVDD2 P Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS. 8 PDSW AO Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register. 9 XTAL1 AI Input 1 for Crystal. 10 XTAL2/CLKIO AI/DI Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADCMODE register in Table 28 for more information. 11 DOUT/RDY DO Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. This pin is a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. 12 DIN DI Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK. 13 SCLK DI Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a Schmitt triggered input, making the interface suitable for opto-isolated applications. |
类似零件编号 - AD7172-4 |
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类似说明 - AD7172-4 |
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