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6PAIC3104IRHBRQ1 数据表(PDF) 59 Page - Texas Instruments |
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6PAIC3104IRHBRQ1 数据表(HTML) 59 Page - Texas Instruments |
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59 / 95 page  59 TLV320AIC3104-Q1 www.ti.com SLAS715A – JUNE 2010 – REVISED MARCH 2016 Product Folder Links: TLV320AIC3104-Q1 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Table 61. Page 0/Register 54: DAC_L1 to HPLCOM Volume Control Register BIT TYPE RESET DESCRIPTION D7 R/W 0 DAC_L1 Output Routing Control 0: DAC_L1 is not routed to HPLCOM. 1: DAC_L1 is routed to HPLCOM. D6–D0 R/W 000 0000 DAC_L1 to HPLCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 51. Table 62. Page 0/Register 55: Reserved Register BIT TYPE RESET DESCRIPTION D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 63. Page 0/Register 56: PGA_R to HPLCOM Volume Control Register BIT TYPE RESET DESCRIPTION D7 R/W 0 PGA_R Output Routing Control 0: PGA_R is not routed to HPLCOM. 1: PGA_R is routed to HPLCOM. D6–D0 R/W 000 0000 PGA_R to HPLCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 51. Table 64. Page 0/Register 57: DAC_R1 to HPLCOM Volume Control Register BIT TYPE RESET DESCRIPTION D7 R/W 0 DAC_R1 Output Routing Control 0: DAC_R1 is not routed to HPLCOM. 1: DAC_R1 is routed to HPLCOM. D6–D0 R/W 000 0000 DAC_R1 to HPLCOM Analog Volume Control For 7-bit register settings versus analog gain values, see Table 51. Table 65. Page 0/Register 58: HPLCOM Output Level Control Register BIT TYPE RESET DESCRIPTION D7–D4 R/W 0000 HPLCOM Output Level Control 0000: Output level control = 0 dB 0001: Output level control = 1 dB 0010: Output level control = 2 dB ... 1000: Output level control = 8 dB 1001: Output level control = 9 dB 1010–1111: Reserved. Do not write these sequences to these register bits. D3 R/W 0 HPLCOM Mute 0: HPLCOM is muted. 1: HPLCOM is not muted. D2 R/W 1 HPLCOM Power-Down Drive Control 0: HPLCOM is weakly driven to a common mode when powered down. 1: HPLCOM is high-impedance when powered down. D1 R 1 HPLCOM Volume Control Status 0: All programmed gains to HPLCOM have been applied. 1: Not all programmed gains to HPLCOM have been applied yet. D0 R/W 0 HPLCOM Power Control 0: HPLCOM is not fully powered up. 1: HPLCOM is fully powered up. Table 66. Page 0/Register 59: Reserved Register BIT TYPE RESET DESCRIPTION D7–D0 R/W 0000 0000 Reserved. Do not write to this register. Table 67. Page 0/Register 60: PGA_L to HPROUT Volume Control Register BIT TYPE RESET DESCRIPTION D7 R/W 0 PGA_L Output Routing Control 0: PGA_L is not routed to HPROUT. 1: PGA_L is routed to HPROUT. D6–D0 R/W 000 0000 PGA_L to HPROUT Analog Volume Control For 7-bit register settings versus analog gain values, see Table 51. |
类似零件编号 - 6PAIC3104IRHBRQ1 |
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类似说明 - 6PAIC3104IRHBRQ1 |
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