SM320VC33, SMJ320VC33

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SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

6.4 Phase-Locked Loop Characteristics Using EXTCLK or On-Chip Crystal Oscillator Timing

Requirements

see

(1) (2)

MIN

MAX

UNIT

Frequency range, PLL input

MHz

Frequency range, PLL output

MHz

PLL current, CVDD supply

mA

PLL power, CVDD supply

mW

PLL output duty cycle at H1

PLLJ

ps

PLL lock time in input cycles

1000

cycles

(1)

(2)

To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high frequencies, this may

require a fast rise and fall time as well as a tightly controlled duty cycle. At lower frequencies, these requirements are less restrictive

when in x1 and x0.5 modes. The PLL, however, must have an input duty cycle of between 40% and 60% for proper operation.

(3)

Not production tested

6.5 Circuit Parameters for On-Chip Crystal Oscillator Timing Requirements

see Figure 2

(1)

MIN

TYP

MAX

UNIT

Oscillator internal supply voltage

V

Fundamental mode frequency range

MHz

DC bias point (input threshold)

50

%VO

Feedback resistance

300

k

Ω

Small signal ac output impedance

500

Ω

85

%VO

85

%VO

(2)

(2)

V

(2)

(2)

V

When used for logic level input, oscillator enabled

(2)

V

When used for logic level input, oscillator enabled

(2)

(2)

V

When used for logic level input, oscillator disabled

V

XOUT internal load capacitance

3

pF

XIN internal load capacitance

3

pF

Delay time, XIN to H1 x1 and x0.5 modes

2

5.5

8

ns

μA

μA

(1)

This circuit is intended for series resonant fundamental mode operation.

(2)

Not production tested

(3)

Signal amplitude is dependent on the crystal and load used.

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