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ADC0858CIN 数据表(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 ADC0858CIN
功能描述  8-Bit Analog Data Acquisition and Monitoring Systems
Download  36 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

ADC0858CIN 数据表(HTML) 4 Page - National Semiconductor (TI)

  ADC0858CIN Datasheet HTML 1Page - National Semiconductor (TI) ADC0858CIN Datasheet HTML 2Page - National Semiconductor (TI) ADC0858CIN Datasheet HTML 3Page - National Semiconductor (TI) ADC0858CIN Datasheet HTML 4Page - National Semiconductor (TI) ADC0858CIN Datasheet HTML 5Page - National Semiconductor (TI) ADC0858CIN Datasheet HTML 6Page - National Semiconductor (TI) ADC0858CIN Datasheet HTML 7Page - National Semiconductor (TI) ADC0858CIN Datasheet HTML 8Page - National Semiconductor (TI) ADC0858CIN Datasheet HTML 9Page - National Semiconductor (TI) Next Button
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DC Electrical Characteristics (Continued)
The following specifications apply for VCC ea5VDC VREF ea45 VDC AGND e DGND e 0V and fOSC e 1 MHz (Rext e
316 kX Cext e 170 pF) unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits apply
at TA e TJ ea25 C
Parameter
Conditions
Typical
Limit
Units
(Note 5)
(Note 6)
(Limits)
DIGITAL CHARACTERISTICS
Logic ‘‘1’’ Input
VCC e 55V
22
V (Min)
Voltage VIH
Logic ‘‘0’’ Input
VCC e 45V
08
V(Max)
Voltage VIL
Logic ‘‘1’’ Input
VIN e VCC
0005
3
m
A (Max)
Current IIH
Logic ‘‘0’’ Input
VIN e 0V
b
0005
b
3
m
A (Max)
Current IIL
Logic ‘‘1’’ Output
VCC e 45V
Voltage VOH
IOUT eb360 mA
24
V (Min)
(Except INT)IOUT eb10 mA
42
V (Min)
Logic ‘‘0’’ Output
IOUT e 16 mA
04
V (Max)
Voltage VOL
VCC e 45V
TRI-STATE Output
CS e Logic ‘‘1’’ (5V)
Current (DO)
VOUT e 04V
b
01
b
3
m
A (Max)
VOUT e 5V
01
3
m
A (Max)
ISOURCE
VOUT Short to GND
b
14
b
65
mA (Min)
(Except INT)
ISINK
VOUT Short to VCC
16
8
mA (Min)
Supply Current ICC
fCLK e 1 MHz
7
10
mA (Max)
ADC0851 or ADC0858
fCLK e 2 MHz
72
mA
(Note 10)
AC Electrical Characteristics
The following specifications apply for VCC ea5VDC VREF ea45 VDC AGND e DGND e 0V fCLK e 1 MHz tr e tf e
5 ns unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits apply at TA e TJ e 25 C
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 5)
(Note 6)
(Limits)
fCLK
Data Clock Frequency
1
2
MHz (Max)
Clock Duty Cycle
40
% (Min)
(Note 11)
60
% (Max)
tSET-UP
CS Falling Edge or
Data Input Valid to
30
70
ns (Min)
CLK Rising Edge
tHOLD
Data Input Valid after
5
30
ns (Min)
CLK Rising Edge
tPD1 tPD0
CLK Rising Edge to
CL e 100 pF
80
200
ns (Max)
Output Data Valid
4


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